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UM0404
The central processing unit (CPU)
programming of the bus cycles (wait-states). The operand and instruction accesses listed
below can extend the execution time of an instruction:
•
Internal IFlash Memory operand reads (same for byte and word operand reads),
•
Internal IRAM operand reads via indirect addressing modes,
•
Internal SFR operand reads immediately after writing,
•
External operand reads,
•
External operand writes,
•
Jumps to non-aligned double word instructions in the internal IFlash Memory space,
•
Testing Branch Conditions immediately after PSW writes.
3.4
CPU special function registers
The CPU requires a set of Special Function Registers (SFRs) to maintain the system state
information, to supply the ALU with register- addressable constants and to control system
and bus configuration, multiply and divide ALU operations, code memory segmentation,
data memory paging, and accesses to the General Purpose Registers and the System
Stack.
The access mechanism for these SFRs in the CPU core is identical to the access
mechanism for any other SFR. Since all SFRs can be controlled by means of any instruction
which is able to address the SFR memory space, a lot of flexibility has been gained without
creating a set of system-specific instructions.
Note, however, that there are user access restrictions for some of the CPU core SFRs to
ensure proper processor operations. The instruction pointer IP and code segment pointer
CSP cannot be accessed directly. They can only be changed indirectly via branch
instructions. The PSW, SP, and MDC registers can be modified, not only explicitly by the
programmer, but also implicitly by the CPU during normal instruction processing.
Table 7. Minimum execution times
Memory area
Instruction fetch
Word instruction
(CPU clock cycles)
Double word instruction
(CPU clock cycles)
Internal Memory (IFlash)
2
2
Internal Memory (XFlash)
2
4
Internal IRAM
6
8
Internal XRAM
2
4
16-bit De-multiplex Bus
2
4
16-bit Multiplexed Bus
3
6
8-bit De-multiplex Bus
4
8
8-bit Multiplexed Bus
6
12