The central processing unit (CPU)
UM0404
54/564
DocID13284 Rev 2
Figure 8. CPU block diagram
3.1 Instruction
pipelines
The instruction pipeline breaks down CPU processing into the four following stages:
•
Fetch: An instruction selected by the Instruction Pointer (IP) and the Code Segment
Pointer (CSP) is fetched from either the internal memory, IRAM, XRAM or external
memory.
•
Decode:
Instructions are decoded and, if required, the operand addresses are
calculated and the respective operands are fetched.
For all instructions, which implicitly access the system stack, the SP register is either
decremented or incremented, as specified.
For branch instructions the Instruction Pointer and the Code Segment Pointer are
updated with the desired branch target address (provided that the branch is taken).
•
Execute:
An operation is performed on the previously fetched operands in the ALU.
Additionally, the condition flags in the PSW register are updated as specified by the
instruction. All explicit writes to the SFR memory space and all auto-increment or auto-
decrement writes to GPRs used as indirect address pointers are performed during the
execute stage of an instruction, too.
CPU
SP
STKOV
STKUN
Execution Unit
Instruction Pointer
4-Stage
Pipeline
PSW
SYSCON
MDH
MDL
Multiplication
Bit-Mask
Barrel-Shift
CP
16-bit
ALU
R15
R0
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Code Segment
Data Page
General
Purpose
Registers
2 Kbyte
Bank n
Bank i
Bank 0
16
16
512 Kbyte
IFlash
64 + 2 Kbyte
32
Division Hardware
Generator
Pointer
Pointers
XRAM
IRAM
320 Kbyte
XFlash
16