Architectural overview
UM0404
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DocID13284 Rev 2
To decrease loop execution overhead, three enhancements have been provided:
1.
Single cycle branch execution is provided after the first iteration of a loop. Therefore,
only one instruction cycle is lost during the execution of the entire loop. In loops which
fall through upon completion, no instruction cycle is lost when exiting the loop. No
special instruction is required to perform loops, and loops are automatically detected
during execution of branch instructions.
2.
Detection of the end of a table avoids the use of two compare instructions embedded in
loops. One simply places the lowest negative number at the end of the specific table,
and specifies branching if neither this value nor the compared value have been found.
Otherwise the loop is terminated if either condition has been met. The terminating
condition can then be tested.
3.
The third loop enhancement provides a more flexible solution than the Decrement and
Skip on Zero instruction which is found in other microcontrollers. Through the use of
Compare and Increment or Decrement instructions, the user can make comparisons to
any value. This allows loop counters to cover any range. This is particularly powerful in
table searching.
Saving of system state is automatically performed on the internal system stack avoiding the
use of instructions to preserve state upon entry and exit of interrupt or trap routines. Call
instructions push the value of the IP on the system stack, and require the same execution
time as branch instructions.
Instructions have also been provided to support indirect branch and call instructions. This
supports implementation of multiple CASE statement branching in assembler macros and
high level languages.
1.1.5
Consistent and optimized instruction formats
To obtain optimum performance in a pipeline design, an instruction set has been designed
using concepts of Reduced Instruction Set Computing (RISC).
These concepts primarily allow fast decoding of the instructions and operands, while
reducing pipeline holds. These concepts, however, do not preclude the use of complex
instructions, which are required by microcontroller users.
The following goals were used to design the instruction set:
•
To provide powerful instructions to perform operations which currently require
sequences of instructions and which are frequently used. To avoid transfer into and out
of temporary registers such as accumulators and carry bit. To perform tasks in parallel
such as saving state upon entry into interrupt routines or subroutines.
•
To avoid complex encoding schemes by placing operands in consistent fields for each
instruction. Also to avoid complex addressing modes which are not frequently used.
This decreases the instruction decode time while also simplifying the development of
compilers and assemblers.
•
To provide most frequently used instructions with one-word instruction formats. All
other instructions are placed into two-word formats. This allows all instructions to be
placed on word boundaries, which alleviates the need for complex alignment hardware.
It also has the benefit of increasing the range for relative branching instructions.
The high performance offered by the hardware implementation of the CPU can efficiently be
used by a programmer via the highly functional ST10F276 instruction set. Possible operand
types are bits, bytes and words. Specific instruction support the conversion (extension) of
bytes to words. A variety of direct, indirect or immediate addressing modes are provided to