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UM0404
Interrupt and trap functions
Depending on where the instructions, source and destination operands are located, there is
a number of combinations. Note, however, that only access conflicts contribute to the delay.
A few examples illustrate these delays:
•
The worst case PEC response time including external accesses will occur, when
instructions N and N+1 are executed out of external memory, instructions N-1 and N
require external operand read accesses and instructions N-3, N-2 and N-1 write back
external operands. In this case the PEC response time is the time to perform seven
word bus accesses.
•
When instructions N and N+1 are executed out of external memory, but all operands for
instructions N-3 through N-1 are in internal memory, then the PEC response time is the
time to perform 1 word bus access plus two CPU clock cycles.
Once a request for PEC service has been acknowledged by the CPU, the execution of the
next instruction is delayed by two CPU clock cycles plus the additional time it might take to
fetch the source operand from internal Flash or external memory and to write the destination
operand over the external bus in an external program environment.
Note:
A bus access in this context also includes delays caused by an external READY signal or by
bus arbitration (HOLD mode).
5.6 External
interrupts
Although the ST10F276 has no dedicated interrupt input pins, it provides many possibilities
to react on external asynchronous events by using a number of I/O lines for interrupt input.
The interrupt function may either be combined with the pin’s main function or may be used
instead of it, if the main pin function is not required. Interrupt signals may be connected to:
•
CC31IO...CC0IO, the capture input / compare output lines of the CAPCOM units,
•
T4IN, T2IN, the timer input pins,
•
CAPIN, the capture input of GPT2.
For each of these pins either a positive, a negative, or both a positive and a negative
external transition can be selected to cause an interrupt or PEC service request. The edge
selection is performed in the control register of the peripheral device associated with the
respective port pin.
The peripheral must be programmed to a specific operating mode to allow generation of an
interrupt by the external signal. The priority of the interrupt request is determined by the
interrupt control register of the respective peripheral interrupt source, and the interrupt
vector of this source will be used to service the external interrupt request.
Note:
In order to use any of the listed pins as external interrupt input, it must be switched to input
mode via its direction control bit DPx.y in the respective port direction control register DPx
(see
).
When port pins CCxIO are used as external interrupt input pins, bit field CCMODx in the
control register of the corresponding capture/compare register CCx must select capture
mode.
When CCMODx is programmed to 001b, the interrupt request flag CCxIR in register CCxIC
will be set on a positive external transition at pin CCxIO.
When CCMODx is programmed to 010b, a negative external transition will set the interrupt
request flag. When CCMODx=011b, both a positive and a negative transition will set the
request flag. In all three cases, the contents of the allocated CAPCOM timer will be latched