Memory organization
UM0404
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DocID13284 Rev 2
Figure 7. Location of the PEC pointers
2.3.4
Special function registers
The functions of the CPU, the bus interface, the I/O ports and the on-chip peripherals of the
ST10F276 are controlled via a number of so-called Special Function Registers (SFRs).
These SFRs are arranged within two areas, each of 512 byte size. The first register block, is
called the SFR area, and is located in the 512 byte above the IRAM (00’FFFFh...00’FE00h),
the second register block, the Extended SFR (ESFR) area, is located in the 512 byte below
the IRAM (00’F1FFh...00’F000h).
Special function registers can be addressed via indirect and long 16-bit addressing modes.
Using an 8-bit offset, together with an implicit base address, makes it possible to address
word SFRs and their respective low byte. This
does not work
for the respective high byte!
Note:
Writing to any byte of an SFR causes the non-addressed complementary byte to be cleared!
The upper half of each register block is bit-addressable, so the respective control/status bit
can be directly modified or checked by using bit addressing. When accessing registers in
the ESFR area using 8-bit addresses or direct bit addressing, an Extend Register (EXTR)
instruction is required before, to switch the short addressing mechanism from the standard
SFR area to the Extended SFR area.
This is not required for 16-bit and indirect addresses. The GPRs R15...R0 are duplicated,
and they are accessible within both register blocks via short 2-, 4- or 8-bit addresses without
switching.
Example:
00’FCFEh
00’FCFCh
00’FCE2h
00’FCE0h
DSTP7
SRCP7
DSTP0
SRCP0
00’F600h
00’FCDEh
00’FCE0h
00’FCFEh
00’FD00h
00’F5FEh
Internal
RAM
PEC
source &
destination
pointers
EXTR
#3
;Switch to ESFR area for the next 3 instructions
MOV
ODP2,
#data16
;this instruction uses 8-bit reg addressing
;(EXTR mandatory)
BSET
DP1h.7
;this instructiion uses direct bit addressing
;(EXTR mandatory)