DocID13284 Rev 2
445/564
UM0404
CAN modules
The configuration of a Message Object is done by programming Mask, Arbitration, Control
and Data field of one of the two interface register sets to the desired values. By writing to the
corresponding IFx Command Request Register, the IFx Message Buffer Registers are
loaded into the addressed Message Object in the Message RAM.
When the
Init
bit in the CAN Control Register is cleared, the CAN Protocol Controller state
machine of the CAN Core and the Message Handler State Machine control the C-CAN’s
internal data flow. Received messages that pass the acceptance filtering are stored into the
Message RAM, messages with pending transmission request are loaded into the CAN
Core’s Shift Register and are transmitted via the CAN bus.
The CPU reads received messages and updates messages to be transmitted via the IFx
Interface Registers. Depending on the configuration, the CPU is interrupted on certain CAN
message and CAN error events.
21.9.2
Message handler state machine
The Message Handler controls the data transfer between the Rx/Tx Shift Register of the
CAN Core, the Message RAM and the IFx Registers.
The Message Handler Finite State Machine (FSM) controls the following functions:
•
Data Transfer from IFx Registers to the Message RAM
•
Data Transfer from Message RAM to the IFx Registers
•
Data Transfer from Shift Register to the Message RAM
•
Data Transfer from Message RAM to Shift Register
•
Data Transfer from Shift Register to the Acceptance Filtering unit
•
Scanning of Message RAM for a matching Message Object
•
Handling of
TxRqst
flags
•
Handling of interrupts
Data Transfer from / to message RAM
When the CPU initiates a data transfer between the IFx Registers and Message RAM, the
Message Handler sets the
Busy
bit in the respective Command Register to ‘1’. After the
transfer has completed, the
Busy
bit is set back to ‘0’ (see
).
The respective Command Mask Register specifies whether a complete Message Object or
only parts of it will be transferred. Due to the structure of the Message RAM, it is not
possible to write single bits/bytes of one Message Object, it is always necessary to write a
complete Message Object into the Message RAM. Therefore the data transfer from the IFx
Registers to the Message RAM requires of a read-modify-write cycle. First, those parts of
the Message Object that are not to be changes are read from the Message RAM, and then
the complete contents of the Message Buffer Registers are written into the Message Object.