ST ST10F276E, User Manual, Page: 460 / 564

CAN modules UM0404
460/564 DocID13284 Rev 2
From two equations above, the new constraints for the CAN system clock tolerance can be
translated in new quality requirements for the oscillator:
It is evident that the PLL jitter imposes a more stringent constraints on oscillator tolerance
than what can be accepted when no PLL is used. ST10F276 PLL characteristics are such
that the oscillator requirements are acceptably impacted by the jitter for the majority of the
worst CAN bus network configurations.
The oscillator tolerance range was increased when the CAN protocol was developed from
version 1.1 to version 1.2 (version 1.0 was never implemented in silicon). The option to
synchronize on edges from dominant to recessive became obsolete, only edges from
recessive to dominant are considered for synchronization. The protocol update to version
2.0 (A and B) had no influence on the oscillator tolerance.
It has to be considered that SJW may not be larger than the smaller of the Phase Buffer
Segments and that the Propagation Time Segment limits the part of the bit time that may be
used for the Phase Buffer Segments.
The combination Prop_Seg = 1 and Phase_Seg1 = Phase_Seg2 = SJW = 4 allows the
largest possible frequency tolerance of 1.58% (in the absence of PLL jitter). This
combination with a Propagation Time Segment of only 10% of the bit time is not suitable for
short bit times; it can be used for bitrates of up to 125 Kbit/s (bit time = 8µs) with a bus
length of 40m.
Configuration of the CAN protocol controller
In most CAN implementations and also in the C-CAN, the bit timing configuration is
programmed in two register bytes. The sum of Prop_Seg and Phase_Seg1 (as TSeg1) is
combined with Phase_Seg2 (as TSeg2) in one byte, SJW and BRP are combined in the
other byte (see
Figure 186 ).
In these bit timing registers (CANxBTR), the four components TSeg1, TSeg2, SJW, and
BRP have to be programmed to a numerical value that is one less than its functional value;
so instead of values in the range of [1...n], values in the range of [0...n-1] are programmed.
That way, for example, SJW (functional range of [1...4]) is represented by only two bits.
Therefore the length of the bit time is (programmed values) [TSeg1 + TSeg2 + 3] t
q
or
(functional values) [Sy Pr Phas Phase_Seg2] t
q
.
df
t
SJW
2
δ ⋅
PLL
–
2 10
t
BT
⋅ ⋅
-------------------------------------
<
df
min t
PB1
t
PB2
( , )
2
δ ⋅
PLL
–
2 13
t
BT
t
PB2
–
⋅ ( ) ⋅
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