Power reduction modes
UM0404
DocID13284 Rev 2
For a request which was programmed for PEC service, a PEC data transfer is performed if
the priority level of this request is higher than the current CPU priority and if the interrupt
system is globally enabled. After the PEC data transfer has been completed the CPU
remains in Idle mode. Otherwise, if the PEC request cannot be serviced because of a too
low priority or a globally disabled interrupt system, the CPU does not remain in Idle mode
but continues program execution with the instruction following the IDLE instruction (see
).
Idle mode can also be terminated by a Non-Maskable Interrupt, with a high to low transition
on the NMI pin. After Idle mode has been terminated by an interrupt or NMI request, the
interrupt system performs a round of prioritization to determine the highest priority request.
In the case of an NMI request, the NMI trap will always be entered.
Any interrupt request whose individual Interrupt Enable flag was set before Idle mode was
entered will terminate Idle mode regardless of the current CPU priority. The CPU will
not
go
back into Idle mode when a CPU interrupt request is detected, even when the interrupt was
not serviced because of a higher CPU priority or a globally disabled interrupt system
(IEN = ‘0’). The CPU will
only
go back into Idle mode when the interrupt system is globally
enabled (IEN = ‘1’)
and
a PEC service on a priority level higher than the current CPU level
is requested and executed.
Figure 210. Transitions between Idle mode and active mode
Note:
An interrupt request which is individually enabled and assigned to priority level 0 will
terminate Idle mode. The associated interrupt vector will not be accessed, however.
The watchdog timer may be used to monitor the Idle mode: an internal reset will be
generated if no interrupt or NMI request occurs before the watchdog timer overflows. To
prevent the watchdog timer from overflowing during Idle mode it must be programmed to a
reasonable duration interval before Idle mode is entered.
24.2 Power
down
mode
To further reduce the power consumption the microcontroller can be switched to Power
Down mode. Clocking of all internal blocks is stopped, the contents of the on-chip RAM
modules, however, are preserved through the voltage supplied via the V
DD
pins (and on-
chip voltage regulator). The watchdog timer is stopped in Power Down mode also. The only
exception could be the Real Time Clock if opportunely programmed and one of the two
oscillator circuits as a consequence (either the main or the low-power on-chip oscillator).
Before entering Power Down mode (by executing the instruction PWRDN), bit VREGOFF in
XMISC register must be set: in this way, as soon as the PWRDN command is executed, the
main voltage regulator is turned off, and only the so called low power voltage regulator
remains active.
Active
Mode
Idle
Mode
IDLE instruction
CPU Interrupt Request
Denied PEC Request
Executed
PEC Request
denied
accepted