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UM0404
Architectural overview
Asynchronous/Synchronous Serial Channels (ASC0 and XASC) and two High-Speed
Synchronous Serial Channels (SSC and XSSC).
They support full-duplex asynchronous communication and half-duplex synchronous
communication. The SSC may be configured so it interfaces with serially linked peripheral
components. Two dedicated Baud rate generators allow to set up all standard Baud rates
without oscillator tuning. For transmission, reception and error handling three separate
interrupt vectors are provided on channel SSC, four vectors are provided on channel ASC0.
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a
start bit and terminated by one or two stop bits. For multiprocessor communication, a
mechanism to distinguish address from data byte has been included (8-bit data plus wake
up bit mode).
In synchronous mode, the ASC0 transmits or receives byte (8-bit) synchronously to a shift
clock which is generated by the ASC0. The SSC transmits or receives characters of 2...16-
bit length synchronously to a shift clock which can be generated by the SSC (master mode)
or by an external master (slave mode). The SSC can start shifting with the LSB or with the
MSB, while the ASC0 always shifts the LSB first. A loop back option is available for testing
purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on transmission
or be checked on reception. Framing error detection allows to recognize data frames with
missing stop bit. An overrun error will be generated, if the last character received has not
been read out of the receive buffer register at the time the reception of a new character is
complete.
The XASC is another USART which is functionally identical with the ASC0. The XASC is an
X-Peripheral (no bit handling) and supports three interrupt vectors. The port line and
interrupt handling is slightly different from that of the ASC0.
Similarly, the XSSC is a Synchronous Serial link functionally identical with the SSC. The
XSSC is an X-Peripheral (no bit handling) and supports three interrupt sources. The port
line and interrupt handling is slightly different from that of the SSC.
1.4.6
General purpose timer (GPT) unit
The GPT unit is a flexible multifunctional timer/counter structure which may be used for time
related tasks, such as event timing and counting, pulse width and duty cycle measurements,
pulse generation, pulse multiplication or incremental interface.
The five 16-bit timers are organized into two separate modules, GPT1 and GPT2. Each
timer in each module may operate independently in a number of different modes, or may be
concatenated with another timer of the same module.
Each timer can be configured individually for one of three basic modes of operation, which
are Timer, Gated Timer, and Counter Mode. In Timer Mode the input clock for a timer is
derived from the internal CPU clock divided by a programmable prescaler, while Counter
Mode allows a timer to be clocked in reference to external events (via TxIN). Pulse width or
duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is
controlled by the ‘gate’ level on its external input pin TxIN.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal (TxEUD) to facilitate for example
position tracking.