DocID13284 Rev 2
117/564
UM0404
Interrupt and trap functions
EXxIN inputs are normally sampled interrupt inputs. However, the interrupt handler circuitry
uses them as level-sensitive inputs. An EXxIN (x = 7...0) Interrupt Enable bit (bit CCxIE in
respective CCxIC register) needs not to be set to properly serve the interrupt request (or
exiting from Power Down mode).
If the Interrupt was enabled (bit CCxIE=’1’ in the respective CCxIC register) before entering
Power Down mode, the device executes the interrupt service routine, and then resumes
execution after the PWRDN instruction. If the interrupt was disabled, the device executes
the instruction following PWRDN instruction, and the Interrupt Request Flag (bit CCxIR in
the respective CCxIC register) remains set until it is cleared by software.
Note:
For CAN1 (and CAN2 when parallel mode is set) the related interrupt control register is
CC8IC; for CAN2 and I
2
C the register is CC9IC.
5.7 X-peripheral
interrupt
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some
constraints on the implementation of the new functionality. In particular, the additional X-
Peripherals XSSC, XASC, I
2
C, XPWM and RTC need some resources to implement
interrupt and PEC transfer capabilities. For this reason, a sophisticated but very flexible
multiplexed structure for the interrupt management is proposed. In
, the principle is
explained through a simple diagram, which shows the basic structure replicated for each of
the four X-interrupt available vectors (XP0INT, XP1INT, XP2INT and XP3INT).
It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each:
•
Byte HighXIRxSEL[15:8]Interrupt Enable bits
•
Byte LowXIRxSEL[7:0]Interrupt Flag bits
When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL
register) define a mask which controls which sources will be associated with the unique
available vector. If more than one source is enabled to issue the request, the service routine
will have to take care to identify the real event to be serviced. This can easily be done by
checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also
provide information about events which are not currently serviced by the interrupt controller
(since masked through the enable bits), allowing an effective software management also in
CANPAR
XI2CEN
CAN2EN
CAN1EN
Interrupt P4.5
Interrupt P4.4
x
0
0
0
No
No
x
0
0
1
Yes (CAN1)
No
x
0
1
0
No
Yes (CAN2)
0
0
1
1
Yes (CAN1)
Yes (CAN2)
1
0
1
1
Yes (CAN1/2)
No
x
1
0
0
No
Yes (I
2
C)
x
1
0
1
Yes (CAN1)
Yes (I
2
C)
x
1
1
0
No
Yes (I
2
C)
0
1
1
1
Yes (CAN1)
Yes (I
2
C)
1
1
1
1
Yes (CAN1/2)
Yes (I
2
C)