ST ST10F276E User Manual Download Page 276

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High-speed synchronous serial interface

UM0404

276/564

DocID13284 Rev 2

Figure 113. Serial clock phase and polarity options

Figure 114. SSC full duplex configuration

Serial Clock

SCLK

Transmit Data

Last

bit

Latch

Data

Shift Data

First

bit

Pins

MTSR / MRST

SSCPO

SSCPH

Shift Register

MTSR

CLK

MRST

Clock

Master

Device #1

Transmit

Receive

Clock

MTSR

MRST

CLK

Clock

Shift Register

Device #2

Slave

MTSR

MRST

CLK

Clock

Shift Register

Device #2

Slave

Summary of Contents for ST10F276E

Page 1: ...ers are listed both by name and hexadecimal address The instruction set is covered in full in the ST10 Family Programming Manual and is therefore not discussed in this manual However software programm...

Page 2: ...pheral event control and interrupt control 28 1 2 2 Memory areas 28 1 2 3 External bus interface 29 1 3 Clock generator 30 1 3 1 PLL operation 31 1 3 2 Prescaler operation 31 1 3 3 Direct drive 31 1 3...

Page 3: ...3 1 4 Particular pipeline effects 56 3 2 Bit handling and bit protection 59 3 3 Instruction execution times 60 3 4 CPU special function registers 61 3 4 1 The system configuration register SYSCON 62 3...

Page 4: ...nit 89 4 2 11 MAC interrupt 90 4 2 12 Number representation rounding 90 4 3 MAC register set 91 4 3 1 Address registers 91 4 3 2 Accumulator control registers 91 4 4 MAC instruction set summary 94 5 I...

Page 5: ...trap 132 5 8 9 Illegal word operand access trap 133 5 8 10 Illegal instruction access trap 133 5 8 11 Illegal external bus access trap 133 6 Parallel ports 134 6 1 Introduction 134 6 1 1 Open drain m...

Page 6: ...ternal data bus width 186 8 2 5 Disable enable control for pin BHE BYTDIS 187 8 2 6 Segment address generation 187 8 2 7 CS signal generation 188 8 2 8 Segment address versus chip select 189 8 3 Progr...

Page 7: ...2 timers and CAPREL 244 10 Asynchronous synchronous serial interface 246 10 1 Asynchronous operation 249 10 2 Synchronous operation 251 10 3 Hardware error detection 253 10 4 ASC0 baud rate generation...

Page 8: ...0 configuration in BSL 305 15 2 3 Booting steps 305 15 2 4 Hardware to activate BSL 306 15 2 5 Memory configuration in bootstrap loader mode 307 15 2 6 Loading the start up code 308 15 2 7 Exiting boo...

Page 9: ...ser alternate mode signature integrity check 322 15 6 9 Alternate boot user software aspects 322 15 6 10 EMUCON register 322 15 6 11 Internal decoding of test modes 323 15 6 12 Example 323 15 7 Select...

Page 10: ...urst mode 361 18 1 4 Single shot mode 362 18 2 XPWM module registers 363 18 3 Interrupt request generation 367 18 4 XPWM output signals 368 19 Analog digital converter 370 19 1 Mode selection and oper...

Page 11: ...on support 413 21 3 1 Configuration examples 414 21 4 Clock Prescaling 416 21 5 CAN module functional overview 417 21 6 Block diagram 418 21 7 Operating modes 418 21 7 1 Software initialization 418 21...

Page 12: ...Real time clock 464 22 1 RTC registers 466 22 1 1 RTCCON RTC control register 466 22 1 2 RTCPH RTCPL RTC prescaler registers 467 22 1 3 RTCDH RTCDL RTC divider counters 468 22 1 4 RTCH RTCL RTC progr...

Page 13: ...al function registers ordered by address 524 26 5 X Registers ordered by name 531 26 6 X Registers ordered by address 536 26 7 Flash registers ordered by name 541 26 8 Flash registers ordered by addre...

Page 14: ...Contents UM0404 14 564 DocID13284 Rev 2 Appendix A Abbreviations 559 Appendix B Document references 560 Revision history 561...

Page 15: ...nctions 149 Table 23 Port3 alternative functions 152 Table 24 Port4 alternate functions 156 Table 25 Port5 alternate functions 162 Table 26 Port6 alternate functions 166 Table 27 Port7 alternate funct...

Page 16: ...IF2 message interface register sets 429 Table 62 Parameters of the CAN bit time 453 Table 63 Reset event definition 472 Table 64 Reset events summary 495 Table 65 PORT0 latched configuration for the...

Page 17: ...ne diagram for interrupt response time 110 Figure 23 Pipeline diagram for PEC response time 112 Figure 24 X Interrupt basic structure 118 Figure 25 SFRs XBUS registers and pins associated with the par...

Page 18: ...BY external circuit 214 Figure 75 SFRs and port pins associated with timer block GPT1 216 Figure 76 GPT1 block diagram 217 Figure 77 Core timer T3 in timer mode 219 Figure 78 Core timer T3 in gated ti...

Page 19: ...low 304 Figure 125 Booting steps for ST10F276 306 Figure 126 Hardware provisions to activate the BSL 307 Figure 127 Memory configuration after reset 308 Figure 128 UART bootstrap loader sequence 310 F...

Page 20: ...nection to one CAN bus with internal parallel mode enabled 416 Figure 176 Block diagram of the C CAN 418 Figure 177 CAN core in silent mode 420 Figure 178 CAN core in loop back mode 421 Figure 179 CAN...

Page 21: ...al reset EA 0 494 Figure 209 PORT0 bits latched into the different registers after reset 497 Figure 210 Transitions between Idle mode and active mode 504 Figure 211 RPD pin external circuit to exit po...

Page 22: ...icated SFRs Additional hardware is provided for a separate multiply and divide unit a bit mask generator and a barrel shifter see Figure 2 Several areas of the processor core have been optimized for p...

Page 23: ...COM2 CAPCOM1 Port 0 Port 1 Port 4 Port 6 Port 5 CPU Core and MAC Unit XCAN2 XSSC XASC XCAN1 XI2C XRAM 2K XRAM 16K XRAM 48K STBY PEC XFLASH 320K IFLASH 512K 32 16 16 16 16 16 16 16 16 16 16 16 PEC Inte...

Page 24: ...g four stage pipeline provides the optimum balancing for the CPU core Fetch In this stage an instruction is fetched from the internal Flash or RAM or from the external memory based on the current IP v...

Page 25: ...ster after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for both signed and unsigned arithmetic is provided through user specifiable b...

Page 26: ...on of multiple CASE statement branching in assembler macros and high level languages 1 1 5 Consistent and optimized instruction formats To obtain optimum performance in a pipeline design an instructio...

Page 27: ...tiple Register Banks This feature allows the user to specify up to sixteen general purpose registers located anywhere in the IRAM A single one instruction cycle instruction is used to switch register...

Page 28: ...y areas The memory space of the ST10F276 is organized as a unified memory which means that code memory data memory registers and I O ports are organized within the same linear address space which cove...

Page 29: ...ernal memory via the external bus interface The integrated External Bus Controller EBC allows flexible access to external memory and or peripheral resources For up to five address areas the bus mode m...

Page 30: ...a crystal or resonator only according to the limited frequency ranges refer to datasheet for more details The resulting internal clock signal is also referred to as CPU clock Two separated clock signa...

Page 31: ...es it remains below the specified value refer to datasheet for details When the PLL is detected no longer locked no longer stable it generates an interrupt request on the PLL Unlock interrupt node Thi...

Page 32: ...e CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current 1 4 On chip peripheral blocks The ST10 family of devices separates peripherals from the...

Page 33: ...Similarly the on chip X Peripherals communicate with the CPU through a dedicated set of registers and dedicated structure of interrupt management system 1 4 2 Peripheral timing Internal operation of...

Page 34: ...configured as inputs The output drivers of three I O ports can be configured pin by pin for push pull operation or open drain operation via control registers During the internal reset all port pins a...

Page 35: ...ll be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete The XASC is another USART which is function...

Page 36: ...time it is serviced by the application software the high byte of the Watchdog Timer is reloaded 1 4 8 Capture compare CAPCOM units The two CAPCOM units support generation and control of timing sequenc...

Page 37: ...t source The port line and interrupt handling is slightly different from that of the standard PWM unit 1 4 10 A D converter A 10 bit A D converter with 16 multiplexed input channels and a sample and h...

Page 38: ...te of 1M Baud The CAN Module uses two pins to interface to a bus transceiver 1 4 12 I2 C serial interface The integrated I2 C Serial Interface handles the transmission and reception of frames over the...

Page 39: ...gs S0TIC S0TBIC S0TIR S0TBIR ASC0 transmit buffer interrupt request flags S0RIC S0EIC S0RIR S0EIR ASC0 receive error interrupt request flags S0CON S0REN ASC0 receiver enable flag SSCTIC SSCRIC SSCTIR...

Page 40: ...y separated memory areas including on chip IFlash IRAM the internal Special Function Register Areas SFRs and ESFRs the address areas for integrated XBUS peripherals and external memory are mapped into...

Page 41: ...2K 512 Data Page 3 Segment 0 16Kbyte 256 XCAN2 9 20 21 22 23 0A 0000 09 FFFF 08 0000 B2F0 11 24 25 26 27 0C 0000 0B FFFF 13 28 29 30 31 0E 0000 0D FFFF B3F1 15 32 33 34 35 0F FFFF 00 F000 CAN1 CAN2 00...

Page 42: ...th the same timing and functionality The IFlash module offers a fast access time allowing zero wait state access with CPU frequency up to 64 MHz Instruction fetches and data operand reads are performe...

Page 43: ...h 00 7FFFh 8K B0F4 01 8000h 01 FFFFh 01 8000h 01 FFFFh 32K B0F5 02 0000h 02 FFFFh 02 0000h 02 FFFFh 64K B0F6 03 0000h 03 FFFFh 03 0000h 03 FFFFh 64K B0F7 04 0000h 04 FFFFh 04 0000h 04 FFFFh 64K B0F8 0...

Page 44: ...e contents of the DPP registers via the PEC source and destination pointers The internal Flash is not provided for single bit storage and therefore it is not bit addressable The first 32 Kbytes of the...

Page 45: ...000 01 FFFF 00 0000 B0F4 B0F5 B0F8 B1F1 00 C000 00 FFFF XCAN1 ESFR SFR IRAM Reserved Ext Memory 00 DFFF 00 E000 00 E7FF 00 E800 00 FDFF 00 FE00 00 F1FF 00 F200 00 F5FF 00 F600 8K 256 512 1K 2K 512 Dat...

Page 46: ...s The general purpose registers GPRs use a block of 16 consecutive words within the IRAM The Context Pointer CP register determines the base address of the currently active register bank This register...

Page 47: ...th the source pointer SRCPx on the lower and the destination pointer DSTPx on the higher word address x 7 0 see Figure 7 on page 48 Whenever a PEC data transfer is performed the pair of source and des...

Page 48: ...byte Note Writing to any byte of an SFR causes the non addressed complementary byte to be cleared The upper half of each register block is bit addressable so the respective control status bit can be...

Page 49: ...on even byte addresses Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for XRAM operands Sequential boundary crossing from...

Page 50: ...d by an external master during hold mode via the ST10F276 s bus interface These external accesses must use the same configuration as the internally programmed No wait states are required The configura...

Page 51: ...y if provided at all These memory areas are the IRAM SFR area the internal Flash Memory the on chip X Peripherals if integrated and the external memory Accessing subsequent data locations that belong...

Page 52: ...be satisfied The EBC is described in Section 8 The external bus interface on page 181 The on chip peripheral units of the ST10F276 are almost independent of the CPU with a separate clock generator Da...

Page 53: ...witched off A transition into an active CPU state is forced by an interrupt if being IDLE or by a reset if being in POWER DOWN mode The IDLE POWER DOWN and RESET states can be entered by particular ST...

Page 54: ...ointer are updated with the desired branch target address provided that the branch is taken Execute An operation is performed on the previously fetched operands in the ALU Additionally the condition f...

Page 55: ...simultaneous processing of up to four instructions Therefore as soon as the pipeline has been filled most instructions appear to be processed during one instruction cycle see Figure 9 on page 55 Speci...

Page 56: ...as the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard interrupt has been processed during the period of time between two following occurrences o...

Page 57: ...struction Therefore to make sure that the new DPPn register value is used at least one instruction must be inserted between a DPPn changing instruction and a subsequent instruction which implicitly us...

Page 58: ...Time critical instruction sequences therefore should not begin directly after the instruction disabling interrupts as shown in the example Note The described delay of 1 instruction also applies for en...

Page 59: ...ses of pipeline configuration extend the instruction processing time by half or by one cycle These cases have to be taken into account for the time critical software routines Besides a general executi...

Page 60: ...ardware protection logic guarantees that only the intended bit s is are effected by the write back operation Note If a conflict occurs between a bit manipulation generated by hardware and an intended...

Page 61: ...eneral Purpose Registers and the System Stack The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can be controlled by means of an...

Page 62: ...nal accesses to XBUS peripherals are disabled 1 XRAM1 and XRAM2 are accessible via the external bus during hold mode External accesses to the other XBUS peripherals are not guaranteed in terms of AC t...

Page 63: ...external interrupts on page 115 or with external reset CSCFG Chip Select Configuration Control 0 Latched Chip Select lines CSx changes 1 TCL after rising edge of ALE 1 Unlatched Chip Select lines CSx...

Page 64: ...e CSP register and the IP are saved to and restored from the stack After reset the segmented memory mode is selected Note Bit SGTDIS controls if the CSP register is pushed onto the system stack in add...

Page 65: ...sses to the on chip 2 Kbyte XRAM are disabled Address range 00 EE00h 00 EEFFh is directed to external memory 1 The on chip 2 Kbyte XRAM is enabled and can be accessed XRAM2EN XRAM2 Enable Bit 0 Access...

Page 66: ...R register the XPEREMU register is a write only register mapped on XBUS memory space address EB7Eh Once the XPEN bit of SYSCON register is set and at least one of the X peripherals except memories is...

Page 67: ...d reserved for emulator software usage User should not write to these registers XEMU0 EB76h XBUS Reset Value xxxxh XEMU1 EB78h XBUS Reset Value xxxxh XEMU2 EB7Ah XBUS Reset Value xxxxh XEMU3 EB7Ch XBU...

Page 68: ...tions the N flag can be interpreted as the sign bit of the result negative N 1 positive N 0 Negative numbers are always represented as the 2 s complement of the corresponding positive number The range...

Page 69: ...te operations 80h to 7Fh otherwise the V flag is cleared The result of an integer addition integer subtraction or 2 s complement is not valid if the V flag indicates an arithmetic overflow For multipl...

Page 70: ...vice routine does not return to the interrupted multiply divide instruction for example in case of a task scheduler that switches between independent tasks the MULIP flag must be saved as part of the...

Page 71: ...ge 23 In case of the segmented memory mode the selected number of segment address bits 7 0 3 0 or 1 0 of register CSP is output on the segment address pins A23 A16 of Port4 for all external code acces...

Page 72: ...sters are implicitly used whenever data accesses to any memory location are made via indirect or direct long 16 bit addressing modes except for override accesses via EXTended instructions and PEC data...

Page 73: ...ve DPP register is output on the segment address pins A23 A19 A17 A16 of Port4 for all external data accesses A DPP register can be updated via any instruction which is capable of modifying an SFR Due...

Page 74: ...ative word Rw or byte Rb GPR address is specified the short 4 bit GPR address is either multiplied by two or not before it is added to the content of register CP see Figure 15 on page 75 Thus both byt...

Page 75: ...igure 15 Implicit CP use by short GPR addressing modes R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 CP 30 CP 28 CP 2 CP IRAM Context Pointer Context Pointer 4 bit GPR Address 1111 Specified b...

Page 76: ...RETURN instructions must not immediately follow an instruction updating the SP register SP FE12h 09h SFR Reset Value FC00h 3 4 11 The stack overflow pointer STKOV This non bit addressable register is...

Page 77: ...instructions and after each addition to the SP register If the content of the SP register is greater than the content of the STKUN register a stack underflow hardware trap will occur Since the least s...

Page 78: ...division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDH must be saved along with registers MDL an...

Page 79: ...ers MDH and MDL to be able to restart the interrupted operation later and then it must be cleared preparing it for the new calculation After completion of the new division or multiplication the state...

Page 80: ...Rev 2 manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ZEROS FF1Ch 8Eh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0...

Page 81: ...anipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ONES FF1Eh 8Fh SFR Reset Value FFFFh Example Mask for FFFFh values used to increment or decr...

Page 82: ...e instructions without penalty CoSTORE instruction for fast access to the MAC SFRs and CoMOV for fast memory to memory table transfer General Two cycle execution for all MAC operations 16 x 16 signed...

Page 83: ...tecture 1 Shared with standard ALU Operand 2 Operand 1 Control Unit Repeat Unit ST10 CPU Interrupt Controller MSW MRW MAH MAL MCW Flags MAE Mux 8 bit Left Right Shifter Mux Mux Sign Extend 16 x 16 Con...

Page 84: ...The new MAC instructions which use IDXi pointers is mostly not capable of using a new IDXi register value which is to be updated by an immediately preceding instruction Thus to make sure that the new...

Page 85: ...the CoMOV instruction The following table shows the various combinations of pointer post modification for each of these two new addressing modes In this document the symbols Rwn and IDXi refer to the...

Page 86: ...cified in the co processor Control Word MCW The product can be shifted one bit left to compensate for the extra sign bit gained in multiplying two 16 bit signed 2 s complement fractional numbers if bi...

Page 87: ...it is accessed as the least significant byte LSB of the MSW register and performs guarding function On MAH write operations the value of the accumulator is automatically adjusted to signed extended 4...

Page 88: ...value depending on the direction of the overflow as well as the arithmetic used The value of the accumulator upon saturation is 00 7FFF FFFFh positive or FF 8000 0000h negative 4 2 8 Data limiter Sat...

Page 89: ...o 31 times or by the content of the Repeat Count bits 12 to 0 in the MAC Repeat Word MRW If the Repeat Count equals N the instruction will be executed N 1 times At each iteration of a cumulative instr...

Page 90: ...case of a MAC interrupt request As the MAC status flags are updated or eventually written by software during the Execute stage of the pipeline the response time of a MAC interrupt request is three in...

Page 91: ...QR0 F004h 02h ESFR Reset Value 0000h QR1 F006h 03h ESFR Reset Value 0000h 4 3 2 Accumulator control registers The MAC unit SFRs include the 40 bit Accumulator MAL MAH and the low byte of MSW and thre...

Page 92: ...1 0 MIR SL E SV C Z N MAE R RW RW RW RW RW RW RW Bit Function MAE Accumulator Extension bits 39 32 N Negative Flag Set when the Accumulator is negative at the end of a MAC operation Z Zero Flag Set w...

Page 93: ...he MAC registers in this CoReg addressing mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIE LM EM VM CM MP MS RW RW RW RW RW RW RW Bit Function MS Saturation Mode When set enables automatic 32 bit satura...

Page 94: ...ress in CoReg addressing mode Registers Description Address MSW MAC Unit Status Word 00000b MAH MAC Unit Accumulator High 00001b MAS limited MAH signed 00010b MAL MAC Unit Accumulator Low 00100b MCW M...

Page 95: ...y accumulate unit MAC CoLOAD 2 CoCMP Rwn Rwm IDXi Rwm Rwn Rwm No CoSHL CoSHR CoASHR CoASHR rnd Rwm data4 Rwm Yes No Yes CoABS Rwn Rwm IDXi Rwm Rwn Rwm No Table 14 MAC instruction set summary continued...

Page 96: ...during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provided for handling erroneous conditions and exce...

Page 97: ...sts all sources that are capable of requesting interrupt or PEC service in the ST10F276 the associated interrupt vectors their locations and the associated trap numbers It also lists the mnemonics of...

Page 98: ...OM Register 28 CC28IR CC28IE CC28INT 00 00E0h 3Ch CAPCOM Register 29 CC29IR CC29IE CC29INT 00 0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00 0114h 45h CAPCOM Register 31 CC31IR CC31IE CC31INT 0...

Page 99: ...able 15 Interrupt and PEC service request sources continued Source of interrupt or PEC service request Request flag Enable flag Interrupt vector Vector location Trap number Table 16 Vector locations a...

Page 100: ...terrupt system register description Interrupt processing is globally controlled by register PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additionally the different in...

Page 101: ...enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect interrupt vector will be generated Upon entry into the interrupt servic...

Page 102: ...nnel number where channel 0 has lowest and channel 8 has highest priority All sources that request PEC service must be programmed to different PEC channels Otherwise an incorrect PEC channel may be ac...

Page 103: ...of the request that is being serviced The PSW is saved on the system stack before The CPU level determines the minimum interrupt priority level that will be serviced Any request on the same or a lower...

Page 104: ...is is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request such as from serial channels or A D converter Each channel is controlled by a...

Page 105: ...nted and the request flag is cleared to indicate that the request has been serviced Continuous transfers are selected by the value FFh in bit field COUNT In this case COUNT is not modified and the res...

Page 106: ...used 5 3 Prioritizing interrupt PEC service requests Interrupt and PEC service requests from all sources can be enabled so they are arbitrated and serviced if they win or they may be disabled so thei...

Page 107: ...nality is built in and handled automatically by the interrupt controller Classes with more than four members can be established by using a number of adjacent interrupt priorities ILVL and the respecti...

Page 108: ...the IP unsegmented or followed by CSP and then IP segmented mode This optimizes the usage of the system stack if segmentation is disabled The CPU priority field ILVL in PSW is updated with the priori...

Page 109: ...th saving and restoring The ST10F276 allows to switch the complete bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction...

Page 110: ...ing of the interrupt request flag N 1 N 2 will be executed after returning from the interrupt service routine Figure 22 Pipeline diagram for interrupt response time The minimum interrupt response time...

Page 111: ...rminated When the above example has the interrupt vector pointing into the internal Flash the interrupt response time is 7 word bus accesses plus 2 CPU clock cycles because fetching of instruction I1...

Page 112: ...U clock cycle of an instruction the minimum PEC response time is four CPU clock cycles The PEC response time is increased by all delays of the instructions in the pipeline that are executed before sta...

Page 113: ...may either be combined with the pin s main function or may be used instead of it if the main pin function is not required Interrupt signals may be connected to CC31IO CC0IO the capture input compare o...

Page 114: ...s external interrupt input pin without affecting peripheral functions When the capture mode enable bit T5SC in register T5CON is cleared to 0 signal transitions on pin CAPIN will only set the interrup...

Page 115: ...duction modes are detailed in Section 24 Power reduction modes on page 502 EXICON F1C0h E0h ESFR Reset Value 0000h These fast external interrupts use the interrupt nodes and vectors of the CAPCOM chan...

Page 116: ...e summarized considering I2 C and CAN2 pin sharing and CAN parallel mode In the table the bits of XPERCON register used to enable disable each module and the bit CANPAR of XMISC register used to enabl...

Page 117: ...PEC transfer capabilities For this reason a sophisticated but very flexible multiplexed structure for the interrupt management is proposed In Figure 24 the principle is explained through a simple dia...

Page 118: ...ters refer to register description section reported just after the table itself Since the XIRxSEL registers are not bit addressable another pair of registers a couple for each XIRxSEL is provided to a...

Page 119: ...rupt request 1 Interrupt request pending FL 2 Interrupt Flag 2 I2 C Receive 0 No interrupt request 1 Interrupt request pending FL 3 Interrupt Flag 0 XSSC Transmit 0 No interrupt request 1 Interrupt re...

Page 120: ...upt Enable 3 XSSC Transmit 0 Interrupt request disabled 1 Interrupt request enabled IE 4 Interrupt Enable 4 XSSC Receive 0 Interrupt request disabled 1 Interrupt request enabled IE 5 Interrupt Enable...

Page 121: ...Writing a 1 will clear the corresponding bit x in XIR0SEL register Writing a 0 has no effect IECLR x Interrupt Enable x CLEAR x 7 0 Writing a 1 will clear the corresponding bit x in XIR0SEL register W...

Page 122: ...ing FL 7 Interrupt Flag 7 XASC Receive 0 No interrupt request 1 Interrupt request pending IE 0 Interrupt Enable 0 CAN2 Interrupt 0 Interrupt request disabled 1 Interrupt request enabled IE 1 Interrupt...

Page 123: ...Flag x SET x 7 0 Writing a 1 will set the corresponding bit x in XIR1SEL register Writing a 0 has no effect IESET x Interrupt Enable x SET x 7 0 Writing a 1 will set the corresponding bit x in XIR1SEL...

Page 124: ...Interrupt request pending FL 6 Interrupt Flag 6 XASC Transmit 0 No interrupt request 1 Interrupt request pending FL 7 Interrupt Flag 7 XASC Receive 0 No interrupt request 1 Interrupt request pending...

Page 125: ...XASC Transmit 0 Interrupt request disabled 1 Interrupt request enabled IE 7 Interrupt Enable 7 XASC Receive 0 Interrupt request disabled 1 Interrupt request enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 126: ...nterrupt request 1 Interrupt request pending FL 2 Interrupt Flag 2 I2C Error 0 No interrupt request 1 Interrupt request pending FL 3 Interrupt Flag 0 XSSC Error 0 No interrupt request 1 Interrupt requ...

Page 127: ...XASC Error 0 Interrupt request disabled 1 Interrupt request enabled IE 5 Interrupt Enable 5 PLL Unlock Oscillator Watchdog 0 Interrupt request disabled 1 Interrupt request enabled IE 6 Interrupt Enabl...

Page 128: ...rdware traps are triggered by events that occur during program execution like illegal access or undefined opcode Software traps are initiated via an instruction within the current execution flow The t...

Page 129: ...trap 5 8 2 Hardware traps Hardware traps are issued by faults or specific system states that occur during the runtime of a program not identified at assembly time A hardware trap may also be triggered...

Page 130: ...l Instruction Access Illegal External Bus Access The bit addressable Trap Flag Register TFR allows a trap service routine to identify the kind of trap which caused the exception Each trap function is...

Page 131: ...uction In this case the occurrence of the class B trap condition is stored in the TFR register but the IP value of the instruction which caused this trap is lost If an Undefined Opcode trap class B oc...

Page 132: ...d opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate non implemented instructions The trap service routine...

Page 133: ...p Whenever a branch is made to an odd byte address the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP value pushed onto the system stack is th...

Page 134: ...auses the output latch and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of...

Page 135: ...the output driver is in the push pull mode If ODPx y is 1 the open drain configuration is selected Note that all ODPx registers are located in the ESFR space see Figure 26 Note When XPWM XASC and XSS...

Page 136: ...Y Y Y Y Y Y Y DP2 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y DP3 Y Y Y Y Y Y Y Y DP4 Y Y Y Y Y Y Y Y DP6 Y Y Y Y Y Y Y Y DP7 Y Y Y Y Y Y Y Y DP8 Threshold Open Drain Control 15 14 13 12 11 10 9 8 7 Y 6 Y 5 Y 4 Y 3...

Page 137: ...resholds for each byte of the indicated ports the 8 bit ports P4 P6 P7 and P8 are controlled by one bit each while ports P0 P1 P2 P3 and P5 are controlled by two bits each PICON F1C4h E2h ESFR Reset V...

Page 138: ...f the XPWM module and of the XASC Port2 is also used for fast external interrupt inputs and for timer 7 input Port3 includes alternate input output functions of timers standard serial interfaces SSC a...

Page 139: ...whether the pin is accessible by the user software or not in the alternate function mode All port lines that are not used for these alternate functions may be used as general purpose I O lines When us...

Page 140: ...o a low level this default can be changed according to the needs of the applications The internal pull up devices are designed such that an external pull down resistors see datasheet specification can...

Page 141: ...outputs the data byte or word see Figure 28 When an external bus mode is enabled the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller...

Page 142: ...nd DP1L P1L FF04h 82h SFR Reset Value 00h P1H FF06h 83h SFR Reset Value 00h Direction Latch Write DP0H y DP0L y Read DP0H y DP0L y Port Output Latch Write P0H y P0L y Read P0H y P0L y Internal Bus MUX...

Page 143: ...des PORT1 outputs the 16 bit intra segment address as an alternate output function During external accesses in multiplexed bus modes when no BUSCON register selects a de multiplexed bus mode PORT1 is...

Page 144: ...3 2 PORT1 analog inputs disturb protection A new register is provided for additional disturb protection support on analog inputs for P1L In particular it allows to disable both the digital input and o...

Page 145: ...y is available and also external memory interface functionality 1 Port line P1 y digital input and output are disabled necessary for input leakage current reduction and to avoid undesired conflict bet...

Page 146: ...y DP1L y Read DP1H y DP1L y Port Output Latch Write P1H y P1L y Read P1H y P1L y Internal Bus MUX 0 1 MUX 0 1 MUX 0 1 1 Input Latch Clock P1H y P1L y Output Buffer y 7 0 Alternate Function Enable Port...

Page 147: ...match occurs the value 1 is written to the port output latch via the line Alternate Data Output When an overflow of the corresponding timer occurs a 0 is written to the port output latch In both cases...

Page 148: ...rces selected from other peripherals for example the CANx controller receive signal CANx_RxD can be used to interrupt the system This new function is controlled using the External Interrupt Source Sel...

Page 149: ...t External Interrupt 0 Input EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External...

Page 150: ...imitations register bit P3 14 is not connected to any output pin P3 FFC4h E2h SFR Reset Value 0000h Open Drain Latch Write ODP2 y Read ODP2 y Direction Latch Write DP2 y Read DP2 y Internal Bus MUX 0...

Page 151: ...11 DP3 10 DP3 9 DP3 8 DP3 7 DP3 6 DP3 5 DP3 4 DP3 3 DP3 2 DP3 1 DP3 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function DP3 y Port direction register DP3 bit y 0 Port line P3 y is an input hig...

Page 152: ...ate function P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 P3 8 P3 9 P3 10 P3 11 P3 12 P3 13 P3 14 P3 15 T0IN CAPCOM1 Timer 0 Count Input T6OUT Timer 6 Toggle Output CAPIN GPT2 Capture Input T3OUT Timer 3 T...

Page 153: ...pective current operating mode The direction must be set accordingly Port3 pins with alternate input output functions are MTSR0 MRST0 RxD0 and SCLK0 Note Enabling the CLKOUT function automatically ena...

Page 154: ...case to ensure floating in hold mode Figure 37 Block diagram of P3 15 CLKOUT and P3 12 BHE WRH pins 6 6 Port4 If this 8 bit port is used for general purpose I O the direction of each line can be confi...

Page 155: ...s of Port4 if any may be used for general purpose I O If segment address lines are selected the alternate function of Port4 may be necessary to access for external memory directly after reset For this...

Page 156: ...alternate functions Port4 Standard function SALSEL 01 64 Kbytes Alternate function SALSEL 11 256 Kbytes Alternate function SALSEL 00 1 Mbyte Alternate function SALSEL 10 16 Mbytes P4 0 P4 1 P4 2 P4 3...

Page 157: ...gure 39 Block diagram of Port4 pins 3 0 Direction Latch Write DP4 y Read DP4 y Port Output Latch Write P4 y Read P4 y Internal Bus MUX 0 1 MUX 0 1 Ext Memory Data Output MUX 0 1 1 Input Latch Clock P4...

Page 158: ...function When CAN parallel mode is selected CAN2_RxD is remapped on P4 5 this occurs only if CAN1 is enabled as well On the contrary if CAN1 is disabled no remapping occurs P4 4 Direction Latch Write...

Page 159: ...pped on P4 5 this occurs only if CAN1 is enabled as well On the contrary if CAN1 is disabled no remapping occurs P4 5 Direction Latch Write DP4 5 Read DP4 5 Port Output Latch Write P4 5 Read P4 5 MUX...

Page 160: ...d on P4 6 this occurs only if CAN1 is enabled as well On the contrary if CAN1 is disabled no remapping occurs MUX 0 1 P4 6 Open Drain Latch Write ODP4 6 Read ODP4 6 Direction Latch Write DP4 6 Read DP...

Page 161: ...emapped on P4 6 this occurs only if CAN1 is enabled as well On the contrary if CAN1 is disabled no remapping occurs 6 7 Port5 This 16 bit input port can only read data There is no output latch and no...

Page 162: ...1P5 10 P5 9 P5 8 P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 R R R R R R R R R R R R R R R R Bit Function P5 y Port data register P5 bit y Read only Table 25 Port5 alternate functions Port5 Pin Alternate...

Page 163: ...A4h D2h SFR Reset Value 0000h P5 15 P5 14 P5 13 P5 12 P5 11 P5 10 P5 9 P5 8 P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 Port5 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Alternat...

Page 164: ...et Value 00h DP6 FFCEh E7h SFR Reset Value 00h ODP6 F1CEh E7h ESFR Reset Value 00h Bit Function P5DIDIS y Port5 Digital Disable register bit y 0 Port line P5 y digital input is enabled Schmitt trigger...

Page 165: ...e can be read from bit field CSSEL in register RP0H read only in order to check the configuration during run time The Table 26 summarizes the alternate functions of Port6 depending on the number of se...

Page 166: ...l is controlled by the pull up devices if activated After reset the CS function must be used if selected so In this case there is no possibility to program any port latches before Thus the alternate f...

Page 167: ...s are enabled via HLDEN also these pins are switched automatically to the appropriate direction Note that the pin drivers for HLDA and BREQ are automatically enabled while the pin driver for HOLD is a...

Page 168: ...e DP6 5 Read DP6 5 Port Output Latch Write P6 5 Read P6 5 MUX 1 0 MUX 1 0 Open Drain Latch Write XODP6 5 Read XODP6 5 Direction Latch Write XDP6 5 Read XDP6 5 Port Output Latch Write XP6 5 Read XP6 5...

Page 169: ...the Port2 lines description As all other capture inputs the capture input function of pins P7 7 P7 4 can also be used as external interrupt inputs with a sample rate of eight CPU clock cycles 15 14 13...

Page 170: ...atches are connected to the internal bus and to the pin driver see Figure 2 on page 24 and Figure 3 on page 30 Pins P7 3 P7 0 POUT3 POUT0 XOR the alternate data output with the port latch output which...

Page 171: ...nternal bus data and alternate data output before the port latch input as do the Port2 pins Open Drain Latch Write ODP7 y Read ODP7 y Direction Latch Write DP7 y Read DP7 y Internal Bus MUX 0 1 Input...

Page 172: ...ODP8 Since in ST10F276 the XPWM or PWM1 and XASC or ASC1 are implemented on P8 0 P8 3 and P8 6 P8 7 respectively when these modules are enabled through the XPERCON register the corresponding bits of...

Page 173: ...11 10 9 8 7 6 5 4 3 2 1 0 P8 7 P8 6 P8 5 P8 4 P8 3 P8 2 P8 1 P8 0 RW RW RW RW RW RW RW RW Bit Function P8 y Port data register P8 bit y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP8 7 DP8 6 DP8 5 DP8 4 D...

Page 174: ...7 P8 0 can also be used as external interrupt inputs with a sample rate of eight CPU clock cycles Bit Function XDP8 y Port direction register bit y y 0 1 2 3 only 0 Port line P8 y is an input high im...

Page 175: ...ompare output ch 18 CC19IO Capture input compare output ch 19 CC20IO Capture input compare output ch 20 CC21IO Capture input compare output ch 21 CC22IO Capture input compare output ch 22 CC23IO Captu...

Page 176: ...ite P8 y Read P8 y MUX 1 0 MUX 1 0 Open Drain Latch Write XODP8 y Read XODP8 y Direction Latch Write XDP8 y Read XDP8 y Port Output Latch Write XP8 y Read XP8 y EXOR XPOUTy Data Output Output Buffer I...

Page 177: ...ins P8 y Open Drain Latch Write ODP8 y Read ODP8 y Direction Latch Write DP8 y Read DP8 y Port Output Latch Write P8 y Read P8 y MUX 1 0 Output Buffer Input Latch Clock CCzIO Data Input I n t e r n a...

Page 178: ...te P8 6 Read P8 6 MUX 1 0 MUX 1 0 Open Drain Latch Write XODP8 6 Read XODP8 6 Direction Latch Write XDP8 6 Read XDP8 6 Port Output Latch Write XP8 6 Read XP8 6 Output Buffer Input Latch Clock XPERCON...

Page 179: ...a general WR signal activated for both byte and word write accesses or specifically control the low byte of an external 16 bit device WRL together with the signal WRH alternate function of P3 12 BHE D...

Page 180: ...o the external crystal When not used the XTAL3 should be tied to ground to avoid spurious consumption while XTAL4 should be left unconnected besides bit OFF32 in RTCCON register should be set 32 kHz o...

Page 181: ...within a specific address area which is defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUSCON4 ADDRSEL4 allow to define four independent address windows while all exte...

Page 182: ...Y Y Y Y Y Y Y ADDRSEL3 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y ADDRSEL4 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y P0L P0H PORT0 Data Registers P1L P1H PORT1 Data Registers DP3 Port3 Direction Control Register P3 Port3...

Page 183: ...entry segmentation active or not segmentation disabled 8 2 1 Multiplexed bus modes In the multiplexed bus modes the 16 bit intra segment address and data use PORT0 The address is time multiplexed wit...

Page 184: ...d The EBC initiates an external access by placing an address on the address bus After a programmable period of time the EBC activates the respective command signal RD WR WRL WRH Data is driven onto th...

Page 185: ...out any overhead but restrict their number to the number of BUSCONs However as BUSCON0 controls all address areas which are not covered by the other BUSCONs this allows to have gaps between these wind...

Page 186: ...control word accesses on an 8 bit data bus as well as byte accesses on a 16 bit data bus Word accesses on an 8 bit data bus are automatically split into two subsequent byte accesses where the low byte...

Page 187: ...ically enabled BYTDIS 0 if a 16 bit data bus is selected during reset otherwise it is disabled BYTDIS 1 It may be disabled if byte access to 16 bit memory is not required and the BHE signal is not use...

Page 188: ...the beginning of each external bus cycle the corresponding valid CS signal is determined and activated All other CS lines are deactivated driven high at the same time Note The CS signals will not be u...

Page 189: ...on the selected CS lines Not selected CS lines will enter the high impedance state and are available for general purpose I O The pull up devices are also active during bus hold on the selected CS lin...

Page 190: ...dge of ALE READY polarity is programmable READY control defines if a bus cycle is terminated internally or externally Programmable chip select timing control Note Internal accesses are executed with m...

Page 191: ...d of time during which the controller s signals do not change The external bus cycles of the ST10F276 can be extended for a memory or a peripheral which cannot keep pace with the controller s maximum...

Page 192: ...the previous bus cycle see Figure 64 During this memory tri state time wait state the CPU is not idle so CPU operations will only be slowed down if a subsequent external instruction or data fetch oper...

Page 193: ...delays With the delay enabled the command s become active half a CPU clock cycle after the falling edge of ALE The read write delay does not extend the memory cycle time and does not slow down the co...

Page 194: ...external device drives READY or READY low in order to indicate that data have been latched write cycle or are available read cycle When the READY or READY function is enabled for a specific address wi...

Page 195: ...he next reset A time out function is only provided by the watchdog timer Combining the READY function with predefined wait states is advantageous in two cases Memory components with a fixed access tim...

Page 196: ...e CS lines can be changed By default after reset the CS lines change half a CPU clock cycle after the rising edge of ALE With the CSCFG bit set in the SYSCON register the CS lines change with the risi...

Page 197: ...in terms of AC timings See Section 2 4 1 XRAM access via external masters on page 50 for additional details VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS perip...

Page 198: ...T 0 CLKOUT disabled pin may be used for general purpose I O 1 CLKOUT enabled pin outputs the system clock signal or a prescaled value of system clock according to XCLKOUTDIV register setting BYTDIS Di...

Page 199: ...rol for BUSCONx 0 With read write delay the CPU inserts 1 TCL after falling edge of ALE 1 No read write delay RW is activated after falling edge of ALE MTTCx Memory Tristate Time Control 0 1 wait stat...

Page 200: ...Read Chip Select Enable 0 The CS signal is independent of the read command RD 1 The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable 0 The CS signal is inde...

Page 201: ...ls The hard wired XADRSx registers are evaluated first A match with one of these registers directs the access to the respective X Peripheral using the corresponding XBCONx register and ignoring all ot...

Page 202: ...pin BHE acts as WRH 1 Pins WR and BHE retain their normal function CSSEL 1 Chip Select Line Selection Number of active CS outputs 0 0 3 CS lines CS2 CS0 0 1 2 CS lines CS1 CS0 1 0 No CS lines at all 1...

Page 203: ...rs like an external peripheral to the controller the respective accesses do not generate valid external bus cycles Due to timing constraints address and write data of an XBUS cycle are reflected on th...

Page 204: ...quences where the external resources are required but cannot be shared with other bus masters In this case the ST10F276 will not answer to HOLD requests from other external masters If HLDEN is cleared...

Page 205: ...devices 8 6 2 Entering the hold state Access to the ST10F276 s external bus is requested by driving its HOLD input low After synchronizing this signal the ST10F276 will complete a current external bus...

Page 206: ...access rights to the ST10F276 by driving the HOLD input high After synchronizing this signal the ST10F276 will drive the HLDA output high actively drive the control signals and resume executing exter...

Page 207: ...ed to support up to three X Peripherals for each peripheral on the XBUS X Peripheral there is a separate address window controlled by an XBCON and an XADRS registers As an interface to a peripheral in...

Page 208: ...XFLASH Bank 2 is no longer available and all accesses to memory range 09 0000h 0B FFFFh are redirected to external memory Visibility of XBUS peripherals In order to keep the ST10F276 compatible with t...

Page 209: ...DocID13284 Rev 2 209 564 UM0404 The external bus interface port pins and interrupts are not occupied by the peripheral the peripheral is then not visible or available Refer to Chapter 26 Register set...

Page 210: ...0D 0000 0C FFFF 10 0B 0000 0A FFFF 8 6 4 05 0000 04 FFFF 07 0000 06 FFFF 09 0000 08 FFFF 2 03 0000 02 FFFF 0 0 B0F0 B0F1 B0F2 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 6...

Page 211: ...FFFF 12 0D 0000 0C FFFF 10 0B 0000 0A FFFF 8 6 4 05 0000 04 FFFF 07 0000 06 FFFF 09 0000 08 FFFF 2 03 0000 02 FFFF 0 0 B0F0 B0F1 B0F2 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57...

Page 212: ...can be accessed XRAM2EN XRAM2 Enable Bit 0 Accesses to the on chip 64 Kbyte XRAM are disabled external access performed Address range 0F 0000h 0F FFFFh is directed to external memory only if XFLASHEN...

Page 213: ...Y that is 16 Kbyte portion of XRAM 32 kHz oscillator Stand by Voltage Regulator and Real Time Clock module is powered by the main VDD This allows to drive low EA pin during reset as requested to confi...

Page 214: ...5 volt 4 0V when RTC and 32 kHz on chip oscillator amplifier are turned off In order to reduce the effect of the current consumption transients on VSTBY pin refer to ISB3 in the Electrical Characteris...

Page 215: ...isters which are used for alternate functions by the GPT1 block are named by Y in Figure 75 All three timers of block GPT1 T2 T3 T4 can run in three basic modes Timer gated timer and counter mode and...

Page 216: ...Y Y T3CON Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y T4CON 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T2IC Y Y Y Y Y Y Y Y T3IC T2 GPT1 Timer 2 Register T3 GPT1 Timer 3 Register T4 GPT1 Timer 4 Register T2IC GPT1 Tim...

Page 217: ...Interrupt Request Interrupt Request T3OUT U D P5 15 P3 7 P3 6 P3 4 P3 5 P5 14 P3 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T3OT L T3OE T3UD E T3UD T3R T3M T3I RW RW RW RW RW RW RW RW RW RW RW Bit Functi...

Page 218: ...he actual count direction as shown in Table 33 If T3UD 0 and pin T3EUD is at low level the timer is counting up With a high level at T3EUD the timer is counting down If T3UD 1 a high level at pin T3EU...

Page 219: ...l purpose I O pin In addition T3OTL can be used in conjunction with the timer over underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timer...

Page 220: ...3 6 must contain 0 see Figure 78 If T3M 0 0 the timer is enabled when T3IN shows a low level A high level at this pin stops the timer If T3M 0 1 pin T3IN must have a high level in order to enable the...

Page 221: ...3 T3IR Interrupt Request T3OTL T3OE T3OUT Up Down XOR 1 0 T3UD T3EUD T3M T3IN P3 3 P3 4 P3 6 T3l T3R MUX T3UDE Core Timer T3 T3IR Interrupt Request T3OTL T3OE T3OUT Up Down XOR 1 0 T3UD T3EUD T3IN Edg...

Page 222: ...according to the speed and the direction of the incremental encoder and its contents therefore always represent the encoder s current position The incremental encoder can be connected directly to the...

Page 223: ...e held high or low for at least eight CPU clock cycles In incremental interface mode the count direction is automatically derived from the sequence in which the input signals change This corresponds t...

Page 224: ...1 2 GPT1 auxiliary timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality They can be configured like timer gated timer or counter mode with the same options for the time...

Page 225: ...r T3 The description and the table apply accordingly Timers T2 and T4 in timer mode or gated timer mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode their opera...

Page 226: ...aused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 For counter operation pin TxIN mus...

Page 227: ...count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T3 can operate in timer gated timer or counter mode in this case...

Page 228: ...gister T2 or T4 and the interrupt request flag T2IR or T4IR is set Note When a T3OTL transition is selected for the trigger signal also the interrupt request flag T3IR will be set upon a trigger indic...

Page 229: ...y timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on a negative transition of T3OTL With this combination the core timer is alterna...

Page 230: ...at the respective auxiliary timer s external input pin TxIN The capture trigger signal can be a positive a negative or both a positive and a negative transition The two least significant bit of bit fi...

Page 231: ...own its interrupt request flag T2IR T3IR or T4IR in register TxIC will be set This will cause an interrupt to the respective timer interrupt vector T2INT T3INT or T4INT or trigger a PEC service if the...

Page 232: ...the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a signal at an external control i...

Page 233: ...Y Y Y Y Y Y Y Y Y Y Y T6CON 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T5IC Y Y Y Y Y Y Y Y T6IC Y Y Y Y Y Y Y Y CRIC Y Y Y Y Y Y Y Y ODP3 Port3 Open Drain Control Register DP3 Port3 Direction Control Reg...

Page 234: ...d Interrupt Request to CAPCOM Timers Capture Clear Interrupt Request P5 11 P5 13 P5 12 P3 2 P5 10 P3 1 T0 T1 T7 T8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6SR T6OTL T6OE T6UDE T6UD T6R T6M T6I RW RW RW...

Page 235: ...shown in the Table 38 If T6UD 0 and pin T6EUD shows a low level the timer is counting up With a high level at T6EUD the timer is counting down If T6UD 1 a high level at pin T6EUD specifies counting up...

Page 236: ...ernal connection is provided for this option An overflow or underflow of timer T6 can also be used to clock the timers in the CAPCOM units For this purpose there is a direct internal connection betwee...

Page 237: ...bit T6R The timer will only run if T6R 1 and the gate is active It will stop if either T6R 0 or the gate is inactive Note A transition of the gate signal at pin T6IN does not cause an interrupt reques...

Page 238: ...ch and no alternate output function The individual configuration for timer T5 is determined by its bit addressable control register T5CON Note that functions which are present in both timers of block...

Page 239: ...ement of the timer can be a positive a negative or both a positive and a negative transition at either the input pin or at the toggle latch T6OTL Bit Function T5I Timer 5 Input Selection Depends on th...

Page 240: ...of auxiliary timer T5 in counter mode Timer concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer...

Page 241: ...an be selected to trigger the capture function or transitions on input T3IN or input T3EUD or both inputs T3IN and T3EUD The active edge is controlled by bit field CI in register T5CON The maximum inp...

Page 242: ...his mode is an overflow or underflow of the core timer T6 When timer T6 overflows from FFFFh to 0000h or when it underflows from 0000h to FFFFh the value stored in register CAPREL is loaded into timer...

Page 243: ...r CAPREL and timer T5 is cleared T5CLR 1 Thus register CAPREL always contains the correct time between two events measured in timer T5 increments Timer T6 which runs in timer mode counting down with a...

Page 244: ...the respective timer or CAPREL interrupt vector T5INT T6INT or CRINT or trigger a PEC service if the respective interrupt enable bit T5IE or T6IE in register TxIC CRIE in register CRIC is set There is...

Page 245: ...245 564 UM0404 The general purpose timer units CRIC FF6Ah B5h SFR Reset Value 00h Note Refer to Chapter 5 1 3 for explanation of the control fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRIR CRIE ILVL...

Page 246: ...s and port pins associated with ASC0 Ports Direction Control Alternate Functions Data Registers 15 14 13 12 11 Y 10 Y 9 8 7 6 5 4 3 2 1 0 ODP3 E S0BG 15 14 13 12 Y 11 Y 10 Y 9 Y 8 Y 7 Y 6 Y 5 Y 4 Y 3...

Page 247: ...onous operation S0STP Number of Stop bit Selection asynchronous operation 0 One stop bit 1 Two stop bit S0REN Receiver Enable bit 0 Receiver disabled 1 Receiver enabled Reset by hardware after recepti...

Page 248: ...ived character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be selected through bit S0OEN When enabled the overrun error status flag S0OE an...

Page 249: ...es either consist of 8 data bits D7 D0 S0M 001b or of 7 data bits D6 D0 plus an automatically generated parity bit S0M 011b Parity may be odd or even depending on bit S0ODD in register S0CON An even p...

Page 250: ...the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that t...

Page 251: ...S0RIR is set after the 9th sample in the last stop bit time slot as programmed regardless whether valid stop bit have been received or not The receive circuit then waits for the next start bit 1 to 0...

Page 252: ...transmission stops Pin TXD0 P3 10 must be configured for alternate data output P3 10 1 and DP3 10 1 in order to provide the shift clock Pin RXD0 P3 11 must also be configured for output P3 11 1 and D...

Page 253: ...rror Asynchronous mode only If the parity error detection enable bit S0PEN is set in parity bit receive modes and the parity check on the received data bit proves false the parity error flag S0PE is s...

Page 254: ...register value for S0BRS 0 and S0BRS 1 Synchronous mode baud rates For synchronous operation the Baud rate generator provides a clock with four times the rate of the established Baud rate The Baud ra...

Page 255: ...last bit of an asynchronous frame is transmitted or after the last bit of a synchronous frame has been transmitted S0RIRis activated when the received frame is moved to S0RBUF While the task of the re...

Page 256: ...in the Figure 104 S0TBIR is an early trigger for the reload routine while S0TIR indicates the completed transmission Software using handshake therefore should rely on S0TIR at the end of a data block...

Page 257: ...t data transfer parity generation and the number of stop bits can be selected Parity framing and overrun error detection is provided to increase the reliability of data transfers Transmission and rece...

Page 258: ...egisters Interrupt Control 15 Y 14 Y 13 Y 12 Y 11 10 Y 9 Y 8 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 Y XS1CON 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XIRxSEL Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y XIRxSET Y Y Y Y Y Y...

Page 259: ...ity 1 Check parity S1FEN Framing Check Enable bit asynchronous operation 0 Ignore framing errors 1 Check framing errors S1OEN Overrun Check Enable bit 0 Ignore overrun errors 1 Check overrun errors S1...

Page 260: ...so reception of a second character may already begin before the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can b...

Page 261: ...void unpredictable behavior of the serial interface XS1TBUF E908h XBUS Reset Value 0000h XS1RBUF E90Ah XBUS Reset Value 00xxh 11 1 Asynchronous operation Asynchronous mode supports full duplex communi...

Page 262: ...t S1PEN always OFF in 8 bit data mode The parity error flag S1PE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit X...

Page 263: ...e coming having the wake up bit cleared The slaves that were not being addressed remain in 8 bit data wake up bit mode ignoring the following data byte see Figure 102 Asynchronous transmission begins...

Page 264: ...the receive interrupt request and an error interrupt request if appropriate Start bit that follow this frame will not be recognized Note In wake up mode received frames are only transferred to the rec...

Page 265: ...serial data transmission stops Pin TXD1 P8 7 must be configured for alternate data output P8 7 1 and DP8 7 1 in order to provide the shift clock Pin RXD1 P8 6 must also be configured for output P8 6...

Page 266: ...ronous mode only If the parity error detection enable bit S1PEN is set in parity bit receive modes and the parity check on the received data bit proves false the parity error flag S1PE is set indicati...

Page 267: ...Baudrate can be calculated for any given clock speed The device datasheet gives a table of values for Baudrate vs reload register value for S1BRS 0 and S1BRS 1 Synchronous mode baud rates For synchro...

Page 268: ...chronous frame has been transmitted Receive RIR internal interrupt signal is activated when the received frame is moved to XS1RBUF While the task of the receive interrupt handler is quite clear the tr...

Page 269: ...chronous synchronous serial interface Figure 110 XASC interrupt generation Idle Idle Start Start Start Stop Stop Stop TBIR TBIR TBIR TIR TIR TIR RIR RIR RIR Idle Idle TBIR TBIR TBIR TIR TIR TIR RIR RI...

Page 270: ...ices Transmission and reception of data is double buffered A 16 bit Baud rate generator provides the SSC with a separate serial clock signal The high speed synchronous serial interface can be configur...

Page 271: ...Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 Y SSCCON 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSCTIC Y Y Y Y Y Y Y Y SSCRIC Y Y Y Y Y Y Y Y SSCEIC Y Y Y Y Y Y Y Y SCLK P3 13 MTSR P3 9 MRST P3 8 ODP3 Port3 Open Drain Contro...

Page 272: ...modes SSCRB F0B2h 59h ESFR Reset Value xxxxh SSCTB F0B0h 58h ESFR Reset Value 0000h SSCCON FFB2h D9h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 273: ...eading clock edge is high to low transition SSCTEN SSC Transmit Error Enable bit 0 Ignore transmit errors 1 Check transmit errors SSCREN SSC Receive Error Enable bit 0 Ignore receive errors 1 Check re...

Page 274: ...BSY will be cleared at the same time Software should not modify SSCBSY as this flag is hardware controlled Only one SSC can be master at a given time The transfer of serial data bit can be programmed...

Page 275: ...state So for an idle high clock the leading edge is a falling one a 1 to 0 transition Figure 113 on page 276 is a summary 12 1 Full duplex operation The different devices are connected through three l...

Page 276: ...re 114 SSC full duplex configuration Serial Clock SCLK Transmit Data Last bit Latch Data Shift Data First bit Pins MTSR MRST SSCPO SSCPH 0 0 1 1 0 1 0 1 Shift Register MTSR CLK MRST Clock Master Devic...

Page 277: ...er SSCTB This value is copied into the shift register which is assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from...

Page 278: ...half duplex configuration only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both pins MTSR and MRST of each device the clock line is co...

Page 279: ...ftware how long a total data frame length can be This option can also be used to interface to byte wide and word wide devices on the same serial bus Note Of course this can only happen in multiples of...

Page 280: ...on The serial channel SSC has its own dedicated 16 bit Baud rate generator with 16 bit reload capability allowing Baud rate generation independent from the timers The Baud rate generator is clocked by...

Page 281: ...ges between one sample before and two samples after the latching edge of the clock signal see Clock Control This condition sets the error flag SSCPE and when enabled via SSCPEN the error interrupt req...

Page 282: ...CRIC controls the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC Each interrupt source also has its own dedicated interrupt vector SCTINT is the transmit interrupt vec...

Page 283: ...Bh SFR Reset Value 00h Note Refer to Section 5 1 3 Interrupt control registers on page 100 for an explanation of the control fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC TIR SSC TIE ILVL GLVL RW R...

Page 284: ...ides the XSSC with a separate serial clock signal The high speed synchronous serial interface can be configured in three ways it can be used with other synchronous serial interfaces the ASC0 XASC in s...

Page 285: ...Y Y Y Y Y XIRxSET Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y SCLK1 P6 5 MTSR1 P6 6 MRST1 P6 7 XSSCBR XSSC Baud Rate Generator Reload Register XSSCTB XSSC Transmit Buffer Register write only XSSCRB XSSC Receive...

Page 286: ...0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC EN 0 SSC MS SSC AREN SSC BEN SSC PEN SSC REN SSC TEN SSC PO SSC PH SSC HB SSCBM RW RW RW RW RW RW RW RW RW RW RW Bit Function programming mode SSCEN 0 S...

Page 287: ...e baudrate errors 1 Check baudrate errors SSCAREN XSSC Automatic Reset Enable bit 0 No additional action upon a baudrate error 1 The XSSC is automatically reset upon a baudrate error SSCMS XSSC Master...

Page 288: ...received Transmit data is written into the Transmit Buffer XSSCTB SSCBE XSSC Baud rate Error Flag 1 More than factor 2 or 0 5 between Slave s actual and expected Baud rate SSCBSY XSSC Busy Flag Set wh...

Page 289: ...ecific values The shift clock can be generated master or received slave This allows the adaptation of the XSSC to a wide range of applications where serial data transfer is required The data width sel...

Page 290: ...ster input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are har...

Page 291: ...data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST1 line to output until it gets a de selection signal or command The slaves...

Page 292: ...and all slaves the content of the shift register is copied into the receive buffer XSSCRB and the receive interrupt flag SSCRIR is set A slave device will immediately output the selected first bit MS...

Page 293: ...rary stations Similar to full duplex mode there are two ways to avoid collisions on the data exchange line Only the transmitting device may enable its transmit pin driver The non transmitting devices...

Page 294: ...tead of the general purpose I O operation the respective port latches have to be set to 1 since the port latch outputs and the alternate output lines are ANDed When an alternate data output line is no...

Page 295: ...error flags to determine the cause of the error interrupt The error flags are not reset automatically but rather must be cleared by software after servicing This allows servicing of some error condit...

Page 296: ...ine in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones so their transmit buffe...

Page 297: ...register that contains the current count Control register for initialization The watchdog timer is a 16 bit up counter which can be clocked with the CPU clock fCPU either divided by 2 or divided by 1...

Page 298: ...e If it is not serviced via the instruction SRVWDT by the time the count reaches FFFFh the watchdog timer will overflow and cause an internal reset This reset will pull the external reset indication p...

Page 299: ...lag of WDTCON register is set if the output voltage of the internal 1 8V supply falls below the threshold typically 1 65V of the Power On detection circuit This circuit is efficient to detect major fa...

Page 300: ...time before the watchdog timer is serviced The Table 43 shows the watchdog time range for 40 MHz and 64 MHz CPU clock PWDT fCPU 2 1 WDTIN x 6 x 216 WDTREL x 28 Table 43 WDTREL reload value Reload val...

Page 301: ...oftware Reset 2 x 0 N Synch Not activated 0 0 0 1 0 x 0 N Synch Not activated 0 0 0 1 0 0 1 Y Synch Not activated 0 0 0 1 0 1 1 Y Synch Activated by internal logic for 1024TCL 0 0 0 1 0 Watchdog Reset...

Page 302: ...oding of reset configuration P0L 5 1 P0L 4 0 will select ST10 standard bootstrap mode Test Flash is active and overlaps user Flash for code fetches from address 00 0000h user Flash is active and avail...

Page 303: ...BSL mode if pin P0L 4 is sampled low at the end of a hardware reset In this case the built in bootstrap loader is activated independently of the selected bus mode The bootstrap loader code is stored i...

Page 304: ...0 No CAN1 RxD 1 No Count 1 Count 5 Stop Timer PT0 Initialize CAN Address FA40h No Stop Timer PT0 Message Received No Address MO15_data0 Address Address 1 Address FAC0h No Glitch on CAN1 RxD Clear Tim...

Page 305: ...standard or alternate ROMEN bit 10 of SYSCON is always set regardless of EA pin level BYTDIS bit 9 of SYSCON is set according to data bus width selection via Port0 configuration XPEN bit set for Boot...

Page 306: ...re upon every hardware reset You may want to use a switchable solution via jumper or an external signal for systems that only temporarily use the bootstrap loader Note CAN alternate function on Port4...

Page 307: ...rtly redirected All code accesses are made from the special Test Flash seen in the range 00 0000h to 00 01FFFh User IFLASH is only available for read and write accesses Test Flash cannot be read nor w...

Page 308: ...rotocol to enhance the integrity of the loaded code or data It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external...

Page 309: ...ew hardware requirements related with the new bootstrap loader External Bus configuration need to have four segment address lines or less keep CAN I Os available Usage of CAN pins P4 5 and P4 6 even i...

Page 310: ...factor with respect to the current CPU clock initializes the serial interface ASC0 accordingly and switches pin TxD0 to output Using this baudrate an acknowledge byte is returned to the host that pro...

Page 311: ...rity of the loaded code or data It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory This process may go...

Page 312: ...not consider the tolerances of oscillators and other devices supporting the serial communication This baudrate deviation is a nonlinear function depending on the CPU clock and the baudrate of the hos...

Page 313: ...0 CAN bootstrap loader sequence The Bootstrap Loader may be used to load the complete application software into ROM less systems it may load temporary software into complete systems for testing or cal...

Page 314: ...cation Using this baudrate an Message Object is configured in order to send an acknowledge frame The ST10F276 will not send this Message Object but the host can request it by sending remote frame The...

Page 315: ...64 instructions may be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40H that is the first loaded instruction The bootstrap loading sequence is now terminated...

Page 316: ...w level on one of these lines a timer is launched that will be stopped when the line gets back to high level For CAN communication the algorithm is made to receive a zero frame i e standard identifier...

Page 317: ...of the CAN Bit Timing register The CAN protocol specification recommends to implement a bit time composed by at least 8 time quantum tq This recommendation have been applied here Moreover the maximum...

Page 318: ...r e2 can be introduced by the division This error is of 1 time quantum maximum To compensate any possible error on bitrate the Re Synchronization Jump Width is fixed to 2 time quanta 15 4 6 How to com...

Page 319: ...6 after the acknowledge Note The CAN boot waits for 128 byte of data instead of 32 see UART boot This is done in order to allow the User to reconfigure the CAN Bitrate as soon as possible 15 5 Compari...

Page 320: ...ap Loader can be started by executing a jump to the address of this routine JMPS 00 xxxx address to be defined User Flash the User Flash is divided in two parts the IFLASH visible only for memory read...

Page 321: ...the clearing of XPEN bit in SYSCON 15 6 5 Watchdog As for standard boot the Watchdog timer should remain disabled during Alternate Boot Mode In case of a Watchdog reset occurs a software reset will be...

Page 322: ...e 09 0000h memory address of operand0 for the signature computing 09 1FFCh memory address of operand1 for the signature computing 09 1FFEh memory address for the signature reference The value for oper...

Page 323: ...ader is enabled and a variable is cleared to indicate that ABM is not enabled If Alternate Boot Mode is selected P0L 5 4 01 then depending on signatures integrity checks a predefined reset sequence is...

Page 324: ...onfigure the Selective Bootstrap Loader to poll only CAN1_RxD no boot via UART other values will let the ST10F276 executing an endless loop into the Test Flash Bit Function 0 UART Selection 0 UART wil...

Page 325: ...s P0L 5 4 01 ABM User Flash Start at 09 0000h Std Bootstrap Loader Jump to Test Flash User Mode User Flash Start at 00 0000h RSTIN 0 to 1 Boot Mode Yes P0L 5 4 10 Software Checks User Reset Vector K1...

Page 326: ...ure the contents of a timer on specific internal or external events or they compare a timer s content with given values and modify output signals in case of a match They support generation and control...

Page 327: ...errupt Control Register T7IC T8ICCAPCOM2 Timer 7 8 Interrupt Control Register Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y DP2 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y P2 Y ODP3 E Y DP3 Y P3 Y Y Y Y ODP7 E Y Y Y Y DP7 Y Y...

Page 328: ...of timer T6 in block GPT2 T0 and T7 may also operate in counter mode from an external input where they can be clocked by external events Each capture compare register may be programmed individually f...

Page 329: ...capture compare registers The basic structure of the four timers is identical while the selection of input signals is different for timers T0 T7 and timers T1 T8 Tx Input Control 2n n 3 10 GPT2 Timer...

Page 330: ...of T01CON controls T1 the low byte of T01CON controls T0 the high byte of T78CON controls T8 the low byte of T78CON controls T7 The control options are identical for all four timers except for extern...

Page 331: ...k divided by a programmable pre scaler The different options of the pre scaler of each timer are selected separately by the bit fields TxI The input frequencies fTx for Tx are determined as a function...

Page 332: ...y other combination the respective timer T1 or T8 will stop When T0 or T7 is programmed to run in counter mode bit field TxI is used to select the count source and transition if the source is the inpu...

Page 333: ...3 Interrupt control registers on page 100 for an explanation of the control fields 16 3 Capture compare registers The 16 bit capture compare registers CC0 through CC31 are used as data registers for...

Page 334: ...e 0000h CCM3 FF58h ACh SFR Reset Value 0000h Capture compare mode registers for the CAPCOM2 unit CC16 CC31 CCM4 FF22h 91h SFR Reset Value 0000h CCM5 FF24h 92h SFR Reset Value 0000h 15 14 13 12 11 10 9...

Page 335: ...r Capture Compare Register CCx The available capture compare modes are listed in the table below ACCx Allocation bit for Capture Compare Register CCx 0 CCx allocated to Timer T0 CAPCOM1 Timer T7 CAPCO...

Page 336: ...cycles before it changes its level During these eight CPU clock cycles the capture input signals are scanned sequentially When a timer is modified or incremented during this process the new timer con...

Page 337: ...pare mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the corresponding mode control register to 100b In this mode the interrupt request flag CCxIR is set each time a...

Page 338: ...r does it disable or enable further compare events In order to use the respective port pin as compare signal output pin CCxIO for compare register CCx in compare mode 1 this port pin must be configure...

Page 339: ...an be used for general purpose I O However after the first match has been detected in this mode all further compare events within the same timer period are disabled for compare register CCx until the...

Page 340: ...1 and also the output pin CCxIO alternate port function will be set to 1 The pin will be reset to 0 when the allocated timer overflows If a match was found for register CCx in this mode all further co...

Page 341: ...re mode 1 will generate interrupt requests but no output function is provided 16 5 5 Double register compare mode In double register compare mode two compare registers work together to control one out...

Page 342: ...e match Note If a match occurs simultaneously for both register CCx and register CCz of the register pair pin CCxIO will be toggled only once but two separate compare interrupt requests will be genera...

Page 343: ...the triggering event occurred see also section External Interrupts Note Each of the 32 capture compare registers CC0 CC31 has its own bit addressable interrupt control register CC0IC CC31IC and its ow...

Page 344: ...h BFh SFR CC19IC F166h B3h ESFR CC4IC FF80h C0h SFR CC20IC F168h B4h ESFR CC5IC FF82h C1h SFR CC21IC F16Ah B5h ESFR CC6IC FF84h C2h SFR CC22IC F16Ch B6h ESFR CC7IC FF86h C3h SFR CC23IC F16Eh B7h ESFR...

Page 345: ...mer In a real application the maximum PWM frequency will depend on the required resolution of the PWM output signal The pulse width modulation module has four independent PWM channels Each channel has...

Page 346: ...IC E Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y PW1 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y PP2 E Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y PW2 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y PP3 E Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y PW3 Y Y Y Y Y Y...

Page 347: ...edge aligned PWM Mode 0 is selected by clearing the respective bit PMx in register PWMCON1 to 0 In this mode the timer PTx of the respective PWM channel is always counting up until it reaches the val...

Page 348: ...eration center aligned PWM Mode 1 is selected by setting the respective bit PMx in register PWMCON1 to 1 In this mode the timer PTx of the respective PWM channel is counting up until it reaches the va...

Page 349: ...om PWM channels 0 and 1 onto the port pin of channel 0 The output of channel 0 is replaced with the logical AND of channels 0 and 1 The output of channel 1 can still be used at its associated output p...

Page 350: ...pped via hardware the respective PTRx bit is cleared The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow registe...

Page 351: ...period PPx the timer start value PTx and the pulse width value PWx appropriately the pulse width tw and the optional pulse delay td may be varied in a wide range see Figure 149 17 2 PWM module regist...

Page 352: ...hen a match is found between counter and PPx shadow register the counter is either reset to 0000h or the count direction is switched from counting up to counting down depending on the selected operati...

Page 353: ...ted by separate control Table 53 PWM module channel specific register addresses Register Address Reg space Register Address Reg space PW0 FE30h 18h SFR PT0 F030h 18h ESFR PW1 FE32h 19h SFR PT1 F032h 1...

Page 354: ...t request flag PWMIR in register PWMIC is set provided that it is enabled via the common interrupt enable bit PWMIE Note The channel interrupt request flags PIRx in register PWMCON0 are not automatica...

Page 355: ...ule However it may be necessary to influence the level of the PWM output pins via software either to initialize the system or to react on some extraordinary condition like a system fault or an emergen...

Page 356: ...4 DocID13284 Rev 2 Figure 150 PWM output signal generation Latch P7 3 PWM 3 Pin P7 3 Latch P7 2 PWM 2 Pin P7 2 Latch P7 1 PWM 1 Pin P7 1 Latch P7 0 PWM 0 Pin P7 0 XOR XOR XOR XOR PWMCON1 PEN3 PWMCON1...

Page 357: ...cation the maximum PWM frequency will depend on the required resolution of the PWM output signal The pulse width modulation module has four independent PWM channels Each channel has a 16 bit up down c...

Page 358: ...XPWM Port Control Register XPPx XPWM Period Register x XPWx XPWM Pulse Width Register x XPTx XPWM Counter Register x XPOLAR XPWM Channel Polarity Register XPOUT0 P8 0 XPOUT1 P8 1 XPOUT2 P8 2 XPOUT3 P8...

Page 359: ...rive 18 1 1 Mode 0 standard PWM generation edge aligned PWM Mode 0 is selected by clearing the respective bit PMx in register XPWMCON1 to 0 In this mode the timer XPTx of the respective XPWM channel i...

Page 360: ...y setting the respective bit PMx in register XPWMCON1 to 1 In this mode the timer XPTx of the respective XPWM channel is counting up until it reaches the value in the associated period shadow register...

Page 361: ...pin of channel 0 The output of channel 0 is replaced with the logical AND of channels 0 and 1 The output of channel 1 can still be used at its associated output pin if enabled Each of the two channels...

Page 362: ...d via hardware the respective PTRx bit is cleared The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register T...

Page 363: ...nd the pulse width value XPWx appropriately the pulse width tW and the optional pulse delay tD may be varied in a wide range see Figure 149 18 2 XPWM module registers The XPWM module is controlled via...

Page 364: ...r XPTx When a match is found between counter and XPPx shadow register the counter is either reset to 0000h or the count direction is switched from counting up to counting down depending on the selecte...

Page 365: ...ster Address Reg space Register Address Reg space XPW0 EC30h XBUS XPT0 EC10h XBUS XPW1 EC32h XBUS XPT1 EC12h XBUS XPW2 EC34h XBUS XPT2 EC14h XBUS XPW3 EC36h XBUS XPT3 EC16h XBUS All XPWM registers are...

Page 366: ...and XPWMCON1CLR XPWMCON1 EC02h XBUS Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET 15 SET 14 SET 13 SET 12 SET 11 SET 10 SET 9 SET 8 SET 7 SET 6 SET 5 SET 4 SET 3 SET 2 SET 1 SET 0 W W W...

Page 367: ...interrupt request flag PIRx of a channel is set at the beginning of a new PWM cycle when loading the shadow registers This indicates that registers XPPx and XPWx are now ready to receive a new value...

Page 368: ...XPERCON is set it is again possible to control the polarity like it is done for the standard PWM on Port7 simply setting or clearing the output data register P8 x x 0 3 maintaining cleared the data re...

Page 369: ...han or equal to the value in XPWx immediately sets the respective output a XPTx value below the XPWx value clears the respective output By clearing or setting the respective Port8 output latch the XPW...

Page 370: ...rocess parameter variations at each reset event The ADC supports the following conversion modes Fixed channel single conversion produces just one result from the selected channel Fixed channel continu...

Page 371: ...Y 11 Y 10 Y 9 Y 8 Y 7 Y 6 5 Y 4 Y 3 Y 2 Y 1 Y 0 Y ADCON 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCIC Y Y Y Y Y Y Y Y ADEIC Y Y Y Y Y Y Y Y AN0 P5 0 AN15 P5 15 P5 Port5 Data Register P5DIDIS Port5 Analo...

Page 372: ...nal register P5DIDIS can be used to further protect ADC input analog section disabling the digital input section Section 6 7 2 Port5 analog inputs disturb protection on page 163 for details on registe...

Page 373: ...ields specify the analog channel to be acted upon the conversion mode and also reflect the status of the converter ADCON FFA0h D0h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VREG OFF...

Page 374: ...er ADDAT or in register ADDAT2 for an injected conversion Note Bit field CHNR of register ADDAT is loaded by the ADC to indicate which channel the result refers to Bit field CHNR of register ADDAT2 is...

Page 375: ...e Stop and restart see above are triggered by bit ADST changing from 0 to 1 ADST must be 0 before being set While a conversion is in progress the mode selection field ADM and the channel selection fie...

Page 376: ...existing channel this corresponds to an unpredictable result since the input of A D Converter is left floating After starting the converter through bit ADST the busy flag ADBSY will be set and the cha...

Page 377: ...While in standard mode continuous conversions are executed at a fixed rate determined by the conversion time in Wait for ADDAT Read Mode there may be delays due to suspended conversions However this...

Page 378: ...in addition to those of Port5 attention must be paid in managing the channel injection mode When the injection is controlled via software the status of bit ADCMUX in register XMISC should be consider...

Page 379: ...ndard or injected will be suspended The temporary register can hold data for ADDAT from a standard conversion or for ADDAT2 from an injected conversion x x 1 x 2 x 3 x 4 Conversion x 1 x x 1 x 3 x 1 W...

Page 380: ...t is immediately set only x x 1 x 2 x 3 Conversion x 1 x x 1 x 2 x 1 Write ADDAT ADDAT Full Read ADDAT x 3 x x 1 x 2 x 3 y Channel Injection Request by CC31 Injected Conversion of Channel y Write ADDA...

Page 381: ...REF pin The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes because the capacitors must reach their final voltage le...

Page 382: ...into a table in the on chip RAM for later evaluation The interrupt request flag ADEIR in register ADEIC will be set either if a conversion result overwrites a previous value in register ADDAT error i...

Page 383: ...irst conversion and for example Wait for Read Mode is entered ADWR bit set the A D Converter is stack waiting for the ADDAT read since the result of the current conversion cannot be immediately writte...

Page 384: ...the center of the bisector line in the actual characteristics Note that for Integral Non Linearity error the effect of offset gain and quantization errors is not included Note Bisector characteristic...

Page 385: ...ernal resistor string in the R C DAC array and by the rest of the analog circuitry An external resistance on VAREF could introduce error under certain conditions for this reasons series resistance are...

Page 386: ...Electrical Characteristics section Input leakage is greatest at high operating temperatures and in general it decreases by one half for each 10 C decrease in temperature Considering that for a 10 bit...

Page 387: ...Figure 165 when the sampling phase is started A D switch close a charge sharing phenomena is installed Figure 166 Charge sharing timing diagram during sampling phase In particular two different trans...

Page 388: ...balance assuming now CS already charged at VA1 The two transients above are not influenced by the voltage source that due to the presence of the RFCF filter is not able to provide the extra charge to...

Page 389: ...m that is for instance 5V assuming to accept a maximum error of half a count 2 44mV it is immediately evident a constraints on CF value In the next section an example of how to design the external net...

Page 390: ...filter with the pole exactly at the maximum frequency of the signal the time constant of the filter is 2 Using the relation between CF and CS and taking some margin 4000 instead of 2048 it is possible...

Page 391: ...alf a count considering the worst case when VA 5V 8 The other conditions to be verified is the time constants of the transients are really and significantly shorter than the sampling period duration T...

Page 392: ...nterface between the microcontroller and a serial I2 C bus It provides both multi master and slave functions and controls all I2 C bus specific sequencing protocol arbitration and timing It supports f...

Page 393: ...cation flow In Master mode it initiates a data transfer and generates the clock signal A serial data transfer always begins with a start condition and ends with a stop condition Both start and stop co...

Page 394: ...ocontroller to read the byte in the Data Register The SCL frequency FSCL is controlled by a programmable clock divider which depends on the I2 C bus mode When the I2 C cell is enabled by setting bit X...

Page 395: ...3 1 Slave mode As soon as a start condition is detected the address is received from the SDA line and sent to the shift register then it is compared with the address of the interface or the General Ca...

Page 396: ...e if the ACK bit is set EVF and BTF bits are set with an interrupt if the ITE bit is set Then the interface waits for a read of the I2CDR register holding the SCL line low see Figure 170 Transfer sequ...

Page 397: ...ress holding the SCL line low see Figure 170 Transfer sequencing EV5 Slave address transmission Then the slave address is sent to the SDA line via the internal shift register In 7 bit addressing mode...

Page 398: ...e Stop condition The interface goes automatically back to slave mode M SL bit cleared Note In order to generate the non acknowledge pulse after the last received data byte the ACK bit must be cleared...

Page 399: ...ta1 A Data2 A DataN NA P EV5 EV6 EV7 EV7 EV7 S Address A Data1 A Data2 A DataN A P EV5 EV6 EV8 EV8 EV8 EV8 S Header A Address A Data1 A DataN A P EV1 EV2 EV2 EV4 Sr Header A Data1 A DataN A P EV1 EV3...

Page 400: ...4 Interrupts There are three different types of interrupt that the module can generate requests related to bus events like start or stop events arbitration lost etc requests related to data transmissi...

Page 401: ...INT Transmit XP0INT XP1INT XP2INT Error XP3INT Refer to Section 5 7 X peripheral interrupt on page 117 for details Table 57 Interrupt event summary Line Interrupt event Event flag Error 10 bit Address...

Page 402: ...is entered I2C SCL line P4 4 can be used to wake up the device from low power mode without resetting it restarting the application from where it was stopped at the execution of PWRDN instruction Agai...

Page 403: ...ode 0 No stop generation 1 Stop generation after the current byte transfer or after the current Start condition is sent The STOP bit is cleared by hardware when the Stop condition is sent In slave mod...

Page 404: ...is bit is set by hardware as soon as the Start condition is generated following a write START 1 An interrupt is generated if ITE 1 It is cleared by software reading I2CSR1 register followed by writing...

Page 405: ...ransmitted It is cleared automatically when BTF is cleared It is also cleared by hardware after detection of Stop condition STOPF 1 loss of bus arbitration ARLO 1 or when the interface is disabled PE...

Page 406: ...The SCL line is not held low while BERR 1 0 No misplaced Start or Stop condition 1 Misplaced Start or Stop condition ARLO Arbitration Lost This bit is set by hardware when the interface loses the arb...

Page 407: ...is set without waiting for the LSB of the address It is cleared by software by reading I2CSR2 and a following write to the I2CCR or by hardware when the interface is disabled PE 0 0 No end of address...

Page 408: ...e interface They are not cleared when the interface is disabled PE 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FR2 FR1 FR0 ADD9 ADD8 RW RW RW RW RW Bit Function ADD 9 8 Interface address These are the mos...

Page 409: ...de The first data byte is received automatically in the I2CDR register using the least significant bit of the address Then the following data bytes are received one by one after reading the I2CDR regi...

Page 410: ...s only word accesses are possible Two waitstates give an access time of 62 5ns 64MHz CPU clock No tristate waitstate is used After reset CAN1 is enabled by default see Reset value of XPERCON register...

Page 411: ...MC EF1Ch CAN1 IF1 Message Control 0000h CAN1IF1DA1 EF1Eh CAN1 IF1 Data A 1 0000h CAN1IF1DA2 EF20h CAN1 IF1 Data A 2 0000h CAN1IF1DB1 EF22h CAN1 IF1 Data B 1 0000h CAN1IF1DB2 EF24h CAN1 IF1 Data B 2 00...

Page 412: ...1M1 EE14h CAN2 IF1 Mask 1 FFFFh CAN2IF1M2 EE16h CAN2 IF1 Mask 2 FFFFh CAN2IF1A1 EE18h CAN2 IF1 Arbitration 1 0000h CAN2IF1A2 EE1Ah CAN2 IF1 Arbitration 2 0000h CAN2IF1MC EE1Ch CAN2 IF1 Message Control...

Page 413: ...sing the same CAN transceiver This configuration is especially supported by providing open drain outputs for the CAN1_Txd and CAN2_TxD signals The open drain function is controlled with the ODP4 regis...

Page 414: ...ne to assign to the pin the active value driven by one of the two for CAN protocol logic level 1 is the recessive state so the non transmitting CAN module allows the other to drive the pin Note that a...

Page 415: ...ure 173 Connection to single CAN bus via one common transceiver CAN1 RX TX CAN_H CAN_L CAN bus CAN2 RX TX XMISC CANPAR 0 CAN CAN Transceiver Transceiver P4 4 P4 7 P4 5 P4 6 5V 2 7k 5V 2 7k OD Open Dra...

Page 416: ...Hz it is recommended to provide the CPU clock divided by 2 to each CAN module 20 MHz is sufficient for CAN module to produce the maximum CAN_H CAN_L CAN bus 1 CAN_H CAN_L CAN bus 2 XMISC CANPAR 0 CAN...

Page 417: ...ction to the physical layer additional external transceiver hardware is required For communication on a CAN network individual Message Objects are configured The Message Objects and Identifier Masks f...

Page 418: ...ting modes 21 7 1 Software initialization The software initialization is started by setting the bit Init in the CAN Control Register either by software or by a hardware reset or by going Bus_Off While...

Page 419: ...ect The CPU may read or write each message any time via the Interface Registers the Message Handler guarantees data consistency in case of concurrent accesses Messages to be transmitted are updated by...

Page 420: ...abled when bit Test is reset to zero 21 7 5 Silent mode The CAN Core can be set in Silent Mode by programming the Test Register bit Silent to one In Silent Mode the C CAN is able to receive valid data...

Page 421: ...input pin is disregarded by the CAN Core The transmitted messages can be monitored at the CAN_TxD pin 21 7 7 Loop back combined with silent mode It is also possible to combine Loop Back Mode and Sile...

Page 422: ...F2 Command Request Register to one the contents of the shift register is stored into the IF2 Registers In Basic Mode the evaluation of all Message Object related control and status bits and of the con...

Page 423: ...x0E reserved 2 CAN Base 0x10 IF1 Command Request 0x0001 CAN Base 0x12 IF1 Command Mask 0x0000 CAN Base 0x14 IF1 Mask 1 0xFFFF CAN Base 0x16 IF1 Mask 2 0xFFFF CAN Base 0x18 IF1 Arbitration 1 0x0000 CAN...

Page 424: ...1h CAN2CR EE00h XBUS Reset Value 0001h CAN Base 0xB0 Message Valid 1 0x0000 read only CAN Base 0xB2 Message Valid 2 0x0000 read only CAN Base 0xB4 0xBE reserved 2 1 r signifies the actual value of the...

Page 425: ...ter enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the busoff recovery sequence Status Register CAN1SR EF02h X...

Page 426: ...es the CPU to monitor the proceeding of the busoff recovery sequence indicating the bus is not stuck at dominant or continuously disturbed 110 CRCError The CRC check sum was incorrect in the message r...

Page 427: ...al state of the Transmit Error Counter Values between 0 and 255 REC 6 0 Receive Error Counter Actual state of the Receive Error Counter Values between 0 and 127 RP Receive Error Passive 0 The Receive...

Page 428: ...med here is used TSeg2 Time segment after the sample point Valid values for TSeg2 are 0h 7h 0 7 The actual interpretation by the hardware of this value is such that one more than the value programmed...

Page 429: ...essage Buffer Registers controlled by their own Command Registers The Command Mask Register specifies the direction of the data transfer and which parts of a Message Object will be transferred The Com...

Page 430: ...N Base 0x22 IF1 Data B 1 CAN Base 0x52 IF2 Data B 1 CAN Base 0x24 IF1 Data B 2 CAN Base 0x54 IF2 Data B 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Busy Message Number R RW 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 431: ...2 1 0 WR RD Mask Arb Control ClrInt Pnd TxRqst NewDat Data A Data B RW RW RW RW RW RW RW RW Bit Function WR RD Write Read 0 Read Transfer data from the Message Object addressed by the Command Request...

Page 432: ...ccess Data Bytes 0 3 0 Data Bytes 0 3 unchanged 1 Transfer Data Bytes 0 3 to IFx Message Buffer Register TxRqst NewDat Access Transmission Request Bit 0 NewDat bit remains unchanged 1 Clear NewDat bit...

Page 433: ...0 Msk 15 0 RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MXtd MDir Msk 28 16 RW RW RW Bit Function Msk 28 0 Identifier Mask Msk 28 18 Identifier Mask Standard Message Msk 28 0 Identifier Mask Extended Mess...

Page 434: ...16 RW RW RW RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID 15 0 RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MsgVal Xtd Dir ID 28 16 RW RW RW RW Bit Function ID 28 0 Message Identifier ID 28 18 Identifier fo...

Page 435: ...2IF1MC EE1Ch XBUS Reset Value 0000h CAN1IF2MC EF4Ch XBUS Reset Value 0000h CAN2IF2MC EE4Ch XBUS Reset Value 0000h Xtd Extended Identifier 0 The standard Identifier 11 bit will be used for this Message...

Page 436: ...Rqst Transmit Request 0 This Message Object is not waiting for transmission 1 The transmission of this Message Object is requested and is not yet done RmtEn Remote Enable 0 At the reception of a Remot...

Page 437: ...st Message Lost only valid for Message Objects with direction receive 0 No message lost since last time this bit was reset by the CPU 1 The Message Handler stored a new message into this object when N...

Page 438: ...bytes of the Message Object will be overwritten by non specified values Message object in the message memory There are 32 Message Objects in the Message RAM To avoid conflicts between CPU access to th...

Page 439: ...e identifier of the message object cannot inhibit the match in the acceptance filtering 1 The corresponding identifier bit is used for acceptance filtering Xtd Extended Identifier 0 The standard Ident...

Page 440: ...ng to a FIFO Buffer this bit must always be set to one For details on the concatenation of Message Objects see Section 21 9 7 Configuration of a FIFO buffer on page 449 NewDat New Data 0 No new data h...

Page 441: ...st be defined the same as in all the corresponding objects with the same identifier at other nodes When the Message Handler stores a data frame it will write the DLC to the value given by the received...

Page 442: ...TR1 EF80h XBUS Reset Value 0000h CAN2TR1 EE80h XBUS Reset Value 0000h CAN1TR2 EF82h XBUS Reset Value 0000h CAN2TR2 EE82h XBUS Reset Value 0000h These registers hold the TxRqst bits of the 32 Message O...

Page 443: ...gisters or by the Message Handler after reception of a Data Frame or after a successful transmission Interrupt pending registers CAN1IP1 EFA0h XBUS Reset Value 0000h CAN2IP1 EEA0h XBUS Reset Value 000...

Page 444: ...f a specific Message Object can be set reset by the CPU via the IFx Message Interface Registers 21 9 CAN application 21 9 1 Management of message objects The configuration of the Message Objects in th...

Page 445: ...rs The Message Handler Finite State Machine FSM controls the following functions Data Transfer from IFx Registers to the Message RAM Data Transfer from Message RAM to the IFx Registers Data Transfer f...

Page 446: ...d The valid Message Object with the highest priority pending transmission request is loaded into the shift register by the Message Handler and the transmission is started The Message Object s NewDat b...

Page 447: ...by the CPU has been received The CPU should reset NewDat bit when it reads the Message Object If at the time of the reception the NewDat bit was already set MsgLst is set to indicate that the previou...

Page 448: ...ked 21 9 4 Updating a transmit object The CPU may update the data bytes of a Transmit Object any time via the IFx Interface registers neither MsgVal nor TxRqst have to be reset before the update Even...

Page 449: ...egister That combination will transfer the whole received message from the Message RAM into the Message Buffer Register Additionally the bits NewDat and IntPnd are cleared in the Message RAM not in th...

Page 450: ...ritten the NewDat bit back to zero Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer is reached If none of the preceding Message Objects is released by writing N...

Page 451: ...ge interrupts the Message Object s interrupt priority decreases with increasing message number A message interrupt is cleared by clearing the Message Object s IntPnd bit The Status Interrupt is cleare...

Page 452: ...ge that is the source of the interrupt may read the message and reset the Message Object s IntPnd at the same time bit ClrIntPnd in the Command Mask Register When IntPnd is cleared the Interrupt Regis...

Page 453: ...in the CAN network The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround the Sample Point The Re Synchronization Jump Width SJW defines how far a resynchronization may move the Sample Point ins...

Page 454: ...this edge delay A_to_B after it has been transmitted B s bit timing segments are shifted with regard to A Node B sends an identifier with higher priority and so it will win the arbitration at a specif...

Page 455: ...d Resynchronization A Hard Synchronization is done once at the start of a frame inside a frame only Resynchronizations occur Hard synchronization After a hard synchronization the bit time is restarted...

Page 456: ...ate for phase errors There are three drawings of each two consecutive bit timings The upper drawing shows the synchronization on a late edge the lower drawing shows the synchronization on an early edg...

Page 457: ...e the Sample Point is shifted after the end of the spike a recessive bus level is sampled In the second example SJW is shorter than the phase error so the Sample Point cannot be shifted far enough the...

Page 458: ...programmable from 1 to 4 time quanta the following condition can be written This expression can be seen as a condition for the CAN system clock tolerance df Considering now that real systems typically...

Page 459: ...illator crystal or resonator The phase error introduced by the PLL jitter is a function of the number of clock periods in particular the jitter increases with the clock period number till a saturation...

Page 460: ...of the bit time that may be used for the Phase Buffer Segments The combination Prop_Seg 1 and Phase_Seg1 Phase_Seg2 SJW 4 allows the largest possible frequency tolerance of 1 58 in the absence of PLL...

Page 461: ...The time after the Sample point that is needed to calculate the next bit to be sent for example data bit CRC bit stuff bit error flag or idle is called the Information Processing Time IPT The IPT is...

Page 462: ...ator or PLL tolerance range should be chosen CAN nodes with different system clocks require different configurations to come to the same bitrate The calculation of the propagation time in the CAN netw...

Page 463: ...q 130 tCPU 5 ns Data from PLL jitter characteristics Tolerance for oscillator no PLL effect 0 35 tq 1 s 2 x tCPU Delay of bus driver 200 ns Delay of receiver circuit 80 ns Delay of bus line 40m 220 ns...

Page 464: ...derived from the on chip oscillator clock XTAL1 input pre divided by a 1 64 fixed counter see Figure 189 This 20 bit counter is loaded at each basic reference clock period with the value of the 20 bit...

Page 465: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit is linked to a function Bit has no function or is not implemented Y Control Registers Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y RTCPL Y Y Y Y RTCDH Y Y Y Y Y Y Y Y Y Y Y Y Y...

Page 466: ...ered every basic clock period the other one is the alarm RTCCON includes an interrupt request flag and an interrupt enable bit for each of them This register is read and written via the XBUS RTCCON ED...

Page 467: ...TC Second Interrupt Request flag 0 the bit was reset less than one basic clock tick ago 1 the interrupt was triggered RTCSEN RTC Second interrupt Enable 0 RTCSI is disabled 1 RTCSI is enabled it is ge...

Page 468: ...Reset Value xxxxh RTCDH ED0Ch XBUS Reset Value xh Note These registers are not reset and are read only The divider works as a decrementor when the internal value reaches 0001h the second interrupt is...

Page 469: ...F of the RTCCON register must be set RTC dividers and counters are stopped to enable a write operation on RTCH or RTCL A write operation on RTCH or RTCL register loads directly the corresponding count...

Page 470: ...L ESFR enables the Port2 alternate sources RTC interrupts are alternate sources 2 and 3 EXISEL F1DAh EDh ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCAL RW 15 14 13 12 11 10 9 8 7 6...

Page 471: ...ource Selection x 7 0 00 Input from associated Port2 pin 01 Input from alternate source 1 10 Input from Port2 pin ORed with alternate source 1 11 Input from Port2 pin ANDed with alternate source 15 14...

Page 472: ...becomes the one imposed by the filter that is 500ns for a CPU clock of 4 MHz 4 TCL is 500ns in this case the minimum from the formula is coherent with the limit imposed by the filter 23 2 Asynchronou...

Page 473: ...t released so the CPU does not start code execution in internal memory Note This is not true if external memory is used pin EA held low during reset phase In this case once RSTIN pin is released and a...

Page 474: ...ounded the device could enter in unpredictable states risking also permanent damages Figure 192 Asynchronous power on RESET EA 1 RSTF P0 15 13 P0 12 2 transparent transparent P0 1 0 not t not transpar...

Page 475: ...in Figure 205 on page 491 Figure 206 on page 492 and Figure 3 on page 30 It occurs when RSTIN is low and RPD is detected or becomes low as well RSTIN P0 15 13 P0 12 2 not t transparent not t P0 1 0 no...

Page 476: ...FLARST 2 TCL RST 1 ms Latching point of Port0 for system start up configuration RPD IBUS CS 1 not transparent not transparent Note 1 Longer than Port0 settling time PLL synchronization if needed that...

Page 477: ...der to properly activate the internal reset logic of the device the RSTIN pin must be held low at least during 4 TCL 2 periods of CPU clock refer also to Section 23 1 Input filter for details on minim...

Page 478: ...a Long Reset is recognized once the 8 TCL are elapsed the P0 15 13 pins becomes transparent so the system clock can be re configured The port returns not transparent 3 4TCL after the internal RSTF si...

Page 479: ...are reset short or long the situation goes immediately to the one illustrated in Figure 194 on page 476 There is no effect if RPD comes again above the input threshold the asynchronous reset is comple...

Page 480: ...ns 50 ns 500 ns 50 ns IBUS CS 7 TCL 1 RSTIN assertion can be released there Refer also to Section 21 1 for details on minimum pulse duration 2 If during the reset condition RSTIN low RPD voltage drop...

Page 481: ...ALE 8 TCL 1 RSTIN assertion can be released there Refer also to Section 21 1 for details on minimum pulse duration 2 If during the reset condition RSTIN low RPD voltage drops below the threshold volta...

Page 482: ...fter Filter RSTIN 1024 8 TCL 4 TCL2 12 TCL 500 ns 50 ns 500 ns 50 ns 500 ns 50 ns IBUS CS 7 TCL 1 If during the reset condition RSTIN low RPD voltage drops below the threshold voltage about 2 5V for 5...

Page 483: ...ce while previously latched bits P0 7 P0 2 are cleared that is written at 1 P0 15 13 not transparent RSTF P0 12 2 transparent not t P0 1 0 not t not transparent RST 1024 8 TCL 3 8 TCL3 1 VRPD 2 5V Asy...

Page 484: ...software resets the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY or if READY is sampled active low after the programmed wait states When READY is...

Page 485: ...04 System reset Figure 200 SW WDT unidirectional RESET EA 1 P0 7 2 not transparent P0 12 8 transparent not t P0 1 0 not t not transparent RST 1024 TCL RSTOUT RSTIN IBUS CS 7 TCL P0 15 13 not transpare...

Page 486: ...led during the initialization routine before EINIT instruction is completed When enabled the open drain of the RSTIN pin is activated pulling down the reset signal for the duration of the internal res...

Page 487: ...l clock speed a short reset may be recognized as a long reset the WDTCON flags are set accordingly Besides when either Software or Watchdog bidirectional reset events occur again when the RSTIN pin is...

Page 488: ...202 SW WDT bidirectional RESET EA 1 P0 15 13 not transparent RSTF P0 12 8 transparent not t P0 1 0 not t not transparent RST 1024 TCL RSTOUT After Filter RSTIN 500 ns 50 ns 500 ns 50 ns IBUS CS 7 TCL...

Page 489: ...onal RESET EA 0 P0 15 13 not transparent RSTF P0 12 8 transparent not t P0 1 0 not t not transparent RST 1024 TCL RSTOUT At this time RSTF is sampled HIGH so SW or WDT Reset is flagged in WDTCON After...

Page 490: ...executed RSTOUT pin is pulled high only when EINIT is executed The RPD pin provides an internal weak pull down resistor which discharges external capacitor at a typical rate of 200 A If bit PWDCFG of...

Page 491: ...the time needed for C0 to be discharged by the internal pull down device then the device is forced in an asynchronous reset This mechanism insures recovery from very catastrophic failure Figure 205 M...

Page 492: ...208 provides additional examples of bidirectional internal reset events Software and Watchdog including in particular the external capacitances charge and discharge transients refer also to Figure 206...

Page 493: ...4 TCL 12 8 us 1 ms C1 charge Tfilter RST 500 ns RPD VIL RST WDTCON 5 0 EINIT 04h 1Ch 00h P0 15 13 4 TCL P0 12 8 P0 7 2 P0 1 0 Latching point Latching point Latching point Latching point not transparen...

Page 494: ...4 TCL 12 8 us 1 ms C1 charge Tfilter RST 500 ns RPD VIL RST WDTCON 5 0 EINIT 04h 1Ch 00h P0 15 13 4 TCL P0 12 8 P0 7 2 P0 1 0 Latching point Latching point Latching point Latching point not transparen...

Page 495: ...ynch 500ns 0 1 1 1 0 Short hardware reset synchronous 1 1 0 N Synch max 4 TCL 500ns 1032 12 TCL max 4 TCL 500ns 0 0 1 1 0 1 1 N Synch max 4 TCL 500ns 1032 12 TCL max 4 TCL 500ns 0 0 1 1 0 1 0 Y Synch...

Page 496: ...nal reset Depending on the reset type different bits are latched When RSTIN goes active the PORT0 configuration input pins are not transparent for the first 1024 TCL After that time only the PORT0 pin...

Page 497: ...3 P0H 2 P0H 1 P0H 0 P0L 7 P0L 6 P0L 5 P0L 4 P0L 3 P0L 2 P0L 1 P0L 0 Software Reset X X X X X X X Watchdog Reset X X X X X X X Synchronous Short Hardware Reset X X X X X X X X X X X X X Synchronous Lon...

Page 498: ...1 1 These bits are set according to Port0 configuration during any reset sequence Write Configuration Control 0 Pins WR acts as WRL pin BHE acts as WRH 1 Pins WR and BHE retain their normal function...

Page 499: ...may control the board s circuitry even though the original ST10F276 remains in its place The original ST10F276 also may resume to control the board after a reset sequence with P0L 1 high Default Adap...

Page 500: ...rded and bit field BTYP of register BUSCON0 is cleared Write configuration P0H 0 Pin P0H 0 WRC selects the initial operation of the control pins WR and BHE during reset When high this pin selects the...

Page 501: ...essing mechanism This allows the restriction of the width of the effective address bus while still deriving CS signals from the complete addresses Default 2 bit segment address A17 A16 allowing access...

Page 502: ...y assumed if present or as soon as it is detected as reference for the Real Time Clock counter and it will be maintained forever unless specifically disabled via software see Section 22 Real time cloc...

Page 503: ...e individual Interrupt Enable flag has been set before the Idle mode was entered regardless of bit IEN For a request selected for CPU interrupt service the associated interrupt service routine is ente...

Page 504: ...abled IEN 1 and a PEC service on a priority level higher than the current CPU level is requested and executed Figure 210 Transitions between Idle mode and active mode Note An interrupt request which i...

Page 505: ...converted Only 8 channels can be managed CANPAR CAN Parallel Mode Selection 0 CAN2 is mapped on P4 4 P4 7 while CAN1 is mapped on P4 5 P4 6 1 CAN1 and CAN2 are mapped in parallel on P4 5 P4 6 This is...

Page 506: ...page 297 or bit pattern within RAM to determine whether the controller was initially switched on or whether it was properly restarted from Power Down mode 24 2 2 Interruptible power down mode This mod...

Page 507: ...before restart the operation when exiting from Power Down especially if the main oscillator was stopped typically when Real Time Clock module is not used or when the low power on chip oscillator circ...

Page 508: ...owing PWRDN instruction and the Interrupt Request Flag bit CCxIR in the respective CCxIC register remains set until it is cleared by software Note Due to internal pipeline the instruction that follows...

Page 509: ...z clock pulses later On the contrary if no oscillation is detected on XTAL3 XTAL4 the reference for the counter will remain the one from the main on chip oscillator XTAL1 XTAL2 Note 1 In case the swit...

Page 510: ...BY and vice versa transition occurs some current flows between VDD and VSTBY pins System noise on both VDD and VSTBY can contribute to increase this phenomenon 24 3 1 Entering stand by mode As already...

Page 511: ...e Power On phase without any temporary glitch The external hardware should be responsible to drive low the RSTIN pin until the VDD is stable even though the internal LVD is active Besides it is reques...

Page 512: ...When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off The Table 67 summa...

Page 513: ...de Low otherwise 2 For multiplexed buses with 8 bit data bus 3 For de multiplexed buses 4 The CS signal that corresponds to the last address remains active low all other enabled CS signals remain inac...

Page 514: ...ter SYSCON by default the CPU clock is output on P3 15 Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON it is possible to program the clock prescaling factor in this way on P3 1...

Page 515: ...gister looks like this REG_NAME A16h A8h SFR ESFR XBUS Reset Value h A byte register looks like this REG_NAME A16h A8h SFR ESFR XBUS Reset Value h Elements 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wr onl...

Page 516: ...R5 CP 10 F5h CPU General Purpose word Register R5 UUUUh R6 CP 12 F6h CPU General Purpose word Register R6 UUUUh R7 CP 14 F7h CPU General Purpose word Register R7 UUUUh R8 CP 16 F8h CPU General Purpose...

Page 517: ...pose registers GPRs bit wise addressing continued Name Physical address 8 bit address Description Reset value Table 70 Special function registers ordered by name Name Physical address 8 bit address De...

Page 518: ...90h 48h CAPCOM Register 8 0000h CC8IC b FF88h C4h CAPCOM Register 8 Interrupt Control Register 00h CC9 FE92h 49h CAPCOM Register 9 0000h CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register...

Page 519: ...ster 00h CC25 FE72h 39h CAPCOM Register 25 0000h CC25IC b F172h E B9h CAPCOM Register 25 Interrupt Control Register 00h CC26 FE74h 3Ah CAPCOM Register 26 0000h CC26IC b F174h E BAh CAPCOM Register 26...

Page 520: ...rection Control Register 00h DPP0 FE00h 00h CPU Data Page Pointer 0 Register 10 bit 0000h DPP1 FE02h 01h CPU Data Page Pointer 1 Register 10 bit 0001h DPP2 FE04h 02h CPU Data Page Pointer 2 Register 1...

Page 521: ...ter Upper half of PORT1 00h P2b FFC0h E0h Port2 Register 0000h P3b FFC4h E2h Port3 Register 0000h P4b FFC8h E4h Port4 Register 8 bit 00h P5b FFA2h D1h Port5 Register read only xxxxh P6b FFCCh E6h Port...

Page 522: ...Register X1 0000h RP0H b F108h E 84h System Start up Configuration Register read only xxh S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Register 0000h S0CON b FFB0h D8h Serial Channel 0 C...

Page 523: ...trol Register 0000h T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register 00h T4 FE44h 22h GPT1 Timer 4 Register 0000h T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h T4IC b FF64h B2h GPT1 Ti...

Page 524: ...TCON b FFAEh D7h Watchdog Timer Control Register 00xxh3 XADRS3 F01Ch E 0Eh XPER Address Select Register 3 800Bh XP0IC b F186h E C3h See Section 5 7 X peripheral interrupt 00h 4 XP1IC b F18Eh E C7h See...

Page 525: ...l Register 00h DP0Hb F102h E 81h P0H Direction Control Register 00h DP1Lb F104h E 82h P1L Direction Control Register 00h DP1Hb F106h E 83h P1H Direction Control Register 00h RP0Hb F108h E 84h System S...

Page 526: ...r 00h ODP3 b F1C6h E E3h Port3 Open Drain Control Register 0000h ODP4 b F1CAh E E5h Port4 Open Drain Control Register 00h ODP6 b F1CEh E E7h Port6 Open Drain Control Register 00h ODP7 b F1D2h E E9h Po...

Page 527: ...gister 0000h T0REL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h MAL FE5Ch 2Eh MAC Unit Accumulator Low Word 0000h MAH FE5Eh 2Fh MAC Unit Accumula...

Page 528: ...S0TBUF FEB0h 58h Serial Channel 0 Transmit Buffer Register write only 0000h S0RBUF FEB2h 59h Serial Channel 0 Receive Buffer Register read only xxxh S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generato...

Page 529: ...8h 94h CAPCOM Mode Control Register 7 0000h PWMCON0 b FF30h 98h PWM Module Control Register 0 0000h PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h T2CON b FF40h A0h GPT1 Timer 2 Control Regis...

Page 530: ...ster 8 Interrupt Control Register 00h CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register 00h CC10IC b FF8Ch C6h CAPCOM Register 10 Interrupt Control Register 00h CC11IC b FF8Eh C7h CAPCOM...

Page 531: ...Register 8 bit 00h DP7b FFD2h E9h Port7 Direction Control Register 00h P8b FFD4h EAh Port8 Register 8 bit 00h DP8b FFD6h EBh Port8 Direction Control Register 00h MRW b FFDAh EDh MAC Unit Repeat Word 0...

Page 532: ...IF2 Message Control 0000h CAN1IP1 EFA0h CAN1 Interrupt Pending 1 0000h CAN1IP2 EFA2h CAN1 Interrupt Pending 2 0000h CAN1IR EF08h CAN1 Interrupt Register 0000h CAN1MV1 EFB0h CAN1 Message Valid 1 0000h...

Page 533: ...IF2DB2 EE54h CAN2 IF2 Data B 2 0000h CAN2IF2M1 EE44h CAN2 IF2 Mask 1 FFFFh CAN2IF2M2 EE46h CAN2 IF2 Mask 2 FFFFh CAN2IF2MC EE4Ch CAN2 IF2 Message Control 0000h CAN2IP1 EEA0h CAN2 Interrupt Pending 1 0...

Page 534: ...Register 2 write only xxxxh XEMU3 EB7Ch XBUS Emulation Register 3 write only xxxxh XIR0CLR EB14h X Interrupt 0 Clear Register write only 0000h XIR0SEL EB10h X Interrupt 0 Selection Register 0000h XIR0...

Page 535: ...h XPWM Module Control Register 0 0000h XPWMCON0CLR EC08h XPWM Module Clear Control Reg 0 write only 0000h XPWMCON0SET EC06h XPWM Module Set Control Register 0 write only 0000h XPWMCON1 EC02h XPWM Modu...

Page 536: ...et value Table 73 X Registers ordered by address Name Physical address Description Reset value XSSCCON E800h XSSC Control Register 0000h XSSCCONSET E802h XSSC Set Control Register write only 0000h XSS...

Page 537: ...terrupt 2 Clear Register write only 0000h XP1DIDIS EB36h PORT1 Digital Disable Register 0000h XIR3SEL EB40h X Interrupt 3 Selection Register 0000h XIR3SET EB42h X Interrupt 3 Set Selection Register wr...

Page 538: ...MPORT EC80h XPWM Module Port Control Register 0000h RTCCON ED00H RTC Control Register 0x00h RTCPL ED06h RTC Prescaler Register Low Byte xxxxh RTCPH ED08h RTC Prescaler Register High Byte xxxxh RTCDL E...

Page 539: ...C EE4Ch CAN2 IF2 Message Control 0000h CAN2IF2DA1 EE4Eh CAN2 IF2 Data A 1 0000h CAN2IF2DA2 EE50h CAN2 IF2 Data A 2 0000h CAN2IF2DB1 EE52h CAN2 IF2 Data B 1 0000h CAN2IF2DB2 EE54h CAN2 IF2 Data B 2 000...

Page 540: ...2 Command Mask 0000h CAN1IF2M1 EF44h CAN1 IF2 Mask 1 FFFFh CAN1IF2M2 EF46h CAN1 IF2 Mask 2 FFFFh CAN1IF2A1 EF48h CAN1 IF2 Arbitration 1 0000h CAN1IF2A2 EF4Ah CAN1 IF2 Arbitration 2 0000h CAN1IF2MC EF4...

Page 541: ...h FCR1L 0x000E 0004 Flash Control Register 1 Low 0000h FDR0H 0x000E 000A Flash Data Register 0 High FFFFh FDR0L 0x000E 0008 Flash Data Register 0 Low FFFFh FDR1H 0x000E 000E Flash Data Register 1 High...

Page 542: ...FCR1H 0x000E 0006 Flash Control Register 1 High 0000h FDR0L 0x000E 0008 Flash Data Register 0 Low FFFFh FDR0H 0x000E 000A Flash Data Register 0 High FFFFh FDR1L 0x000E 000C Flash Data Register 1 Low...

Page 543: ...d size identifier Programming voltage description IDMANUF F07Eh 3Fh ESFR Reset Value 0403h IDCHIP F07Ch 3Eh ESFR Reset Value 114xh IDMEM F07Ah 3Dh ESFR Reset Value 30D0h 15 14 13 12 11 10 9 8 7 6 5 4...

Page 544: ...of IDMEM register when both bits are read low the Flash initialization is complete so all Identification Register bits are correct Before Flash initialization completion the default setting of the dif...

Page 545: ...ers or explicitly load and store external data The ST10F276 provides a unified memory architecture and its on chip hardware automatically detects accesses to IRAM GPRs and SFRs Multiplication and divi...

Page 546: ...ltiplication or division The old MDC contents must be popped from the stack before the RETI instruction is executed For a division the user must first move the dividend into the MD register If a 16 by...

Page 547: ...k operations The ST10F276 supports two types of stacks The system stack is used implicitly by the controller and is located in the IRAM The user stack provides stack access to the user in either the i...

Page 548: ...must be saved into external memory to create space for further stack pushes This is called stack flushing When executing a number of return or pop instructions the upper boundary since the stack empt...

Page 549: ...push operation The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the internal stack...

Page 550: ...values are then tested in the stack underflow and overflow trap routines when moving data Set the stack overflow pointer STKOV to the limit of the defined internal stack area plus six words for the re...

Page 551: ...e old bank and enters a new register bank Each register bank may assign up to 16 registers Each register bank should be allocated during coding based on the needs of each task Once the internal memory...

Page 552: ...a new set of local registers by executing the SCXT switch context instruction This mechanism does not provide a method to recursively call a subroutine Saving and restoring of registers To provide loc...

Page 553: ...PSW decrease the number of overhead instructions executed in the loop Two examples below illustrate searching of ordered and non ordered tables respectively Note The last entry in the table must be g...

Page 554: ...ruction sequences are used 27 6 Floating point support All floating point operations are performed using software Standard multiple precision instructions are used to perform calculations on data type...

Page 555: ...will enter the pipeline except the one that follows the ATOMIC instruction and no interrupt request will be serviced in between All instructions requiring multiple cycles or hold states are regarded a...

Page 556: ...witching to the ESFR area and data page overriding is checked by the development tools or handled automatically Nested locked sequences Each of the described extension instruction and the ATOMIC instr...

Page 557: ...of the IFlash memory All other parts of the IFlash memory addresses 01 8000h 08 FFFFh remain unaffected The SGTDIS Segmentation Disable Enable must also be set to 0 to allow the use of the full on chi...

Page 558: ...h mapping will at the earliest become valid for the second instruction after the instruction which has changed the Flash mapping To enable accesses to the Flash after mapping a branch to the newly sel...

Page 559: ...rnal Bus Controller ESFR Extended Special Function Register FIFO First In First Out Flash Non volatile memory that may be electrically erased FSM Finite State Machine GPR General Purpose Register GPT...

Page 560: ...564 DocID13284 Rev 2 Appendix B Document references 1 16 bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM ST10F276E DocID12303 2 16 bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kb...

Page 561: ...04 0 4 Table 58 on page 411 updated with correct registers address of CAN2 module EExxh instead of EFxxh Table 61 on page 429 updated adding BRP BRPE extedend prescaler option System clock tolerance r...

Page 562: ...L multiplication factors x8 and x10 swapped Table Header updated replacing LP OSC with 32 kHz Table 65 on page 497 Section 24 2 Power down mode on page 504 Voltage Regulator in Power Down description...

Page 563: ...ription updated Section 23 System reset on page 472 Some occurences of EA corrected in EA Section 23 2 Asynchronous reset on page 472 Note in Power On Reset paragraph updated missing word added Sectio...

Page 564: ...TUAL PROPERTY RIGHT ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVI...

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Summary of Contents for ST10F276E

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