High-speed synchronous serial interface
UM0404
DocID13284 Rev 2
Figure 112. Synchronous serial channel SSC block diagram
The operating mode of the serial channel SSC is controlled by its bit-addressable control
register SSCCON. This register serves for two purposes:
•
During programming (SSC disabled by SSCEN = ‘0’) it provides access to a set of
control bit.
•
During operation (SSC enabled by SSCEN = ‘1’) it provides access to a set of status
flags. Register SSCCON is shown below in each of the two modes.
SSCRB (F0B2h / 59h)
ESFR
Reset Value: xxxxh
SSCTB (F0B0h / 58h)
ESFR
Reset Value: 0000h
SSCCON (FFB2h / D9h)
SFR
Reset Value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSC
EN=0
SSC
MS
-
SSC
AREN
SSC
BEN
SSC
PEN
SSC
REN
SSC
TEN
-
SSC
PO
SSC
PH
SSC
HB
SSCBM
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Baud Rate Generator
SSC Control
Block
Internal Bus
Clock Control
CPU
Clock
Slave Clock
Master Clock
SCLK
Shift
Clock
Status
Control
Receive Interrupt Request
Transmit Interrupt Request
Error Interrupt Request
16-bit Shift Register
Pin
Control
MTSR
MRST
Transmit Buffer
Register SSCTB
Receive Buffer
Register SSCRB
P3.13
P3.9
P3.8