DocID13284 Rev 2
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UM0404
System reset
Figure 209. PORT0 bits latched into the different registers after reset
Table 65. PORT0 latched configuration for the different reset events
X : Pin is sampled
- : Pin is not sampled
PORT0
Cl
o
c
k
Op
ti
o
n
s
Seg
m
. A
ddr
.
L
ine
s
Ch
ip
S
e
le
ct
s
WR c
o
n
fi
g
.
B
u
s Ty
pe
R
e
se
rv
ed
BSL
R
e
se
rv
ed
R
e
se
rv
ed
A
d
ap
t Mo
de
Emu M
o
d
e
Sample event
P0
H
.7
P0
H
.6
P0
H
.5
P0
H
.4
P0
H
.3
P0
H
.2
P0
H
.1
P0
H
.0
P0
L.
7
P0
L.
6
P0
L.
5
P0
L.
4
P0
L.
3
P0
L.
2
P0
L.
1
P0
L.
0
Software Reset
-
-
-
X
X
X
X
X
X
X
-
-
-
-
-
-
Watchdog Reset
-
-
-
X
X
X
X
X
X
X
-
-
-
-
-
-
Synchronous Short Hardware Reset
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
Synchronous Long Hardware Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Asynchronous Hardware Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Asynchronous Power-On Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L.5 L.4 L.3 L.2 L.1 L.0
H.
H.
H.
H.
L.7 L.6
H.
H.
H.
H.
RP0H
Clock Port4
Logic
Port6
Logic
SYSCON
BUSCON0
Internal Control Logic
7
6
2
P0L.7
P0L.7
7
9
BYTDIS
WRCFG
PORT0
Bootstrap Loader
Generator
10
9
EA / VSTBY
ROMEN
10