ST ST10F276E, User Manual, Page: 480 / 564

System reset UM0404
480/564 DocID13284 Rev 2
Figure 196. Synchronous short / long hardware RESET (EA = 1)
P0[15:13] not transparent
RSTF
P0[12:2]
transparent not t.
P0[1:0]
not t.
not transparent
FLARST
RST
≤
1 ms
1024 TCL
≤
2 TCL
2)
V
RPD
> 2.5V Asynchronous Reset not entered
200
μ
A Discharge
RPD
RSTOUT
At this time RSTF is sampled HIGH or LOW
so it is SHORT or LONG reset
(After Filter)
RSTIN
< 1032 TCL
≤
4 TCL
4)
3)
≤
12 TCL
1)
≤
500 ns
≥
50 ns
≤
500 ns
≥
50 ns
≤
500 ns
≥
50 ns
IBUS-CS
7 TCL
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),
the asynchronous reset is then immediately entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software.
Bit BDRSTEN is cleared after reset.
4. Minimum RSTIN low pulse duration should also be longer than 500ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).
Notes:
(Internal)
8 TCL
not t.