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UM0404
The external bus interface
8
The external bus interface
The on-chip peripherals and the on-chip RAM and Flash Memory only cover a small fraction
of the ST10F276 address space. The external bus interface gives access to external
peripherals and additional volatile and non-volatile memory. It provides a number of
configurations and can be tailored to fit perfectly into a given application system.
Accesses to external memory or peripherals are executed by the integrated External Bus
Controller (EBC). The function of the EBC is controlled via the SYSCON register and the
BUSCONx and ADDRSELx registers. The BUSCONx registers specify the external bus
cycles in terms of address (mux/demux), data (16-bit/8-bit), chip selects and length (wait-
states / READY control / ALE / RW delay). These parameters are used for accesses within a
specific address area which is defined via the corresponding register ADDRSELx. The four
pairs BUSCON1/ADDRSEL1...BUSCON4/ADDRSEL4 allow to define four independent
“address windows”, while all external accesses outside these windows are controlled via
register BUSCON0.
8.1
Single chip mode
Single chip mode is entered, when pin EA is high during reset. In this case register
BUSCON0 is initialized with 0000h, which also resets bit BUSACT0, so no external bus is
enabled.
In single chip mode the ST10F276 operates only with and out of internal resources. No
external bus is configured and no external peripherals and/or memory can be accessed.
Also no port lines are occupied for the bus interface.
When running in single chip mode, however, external access may be enabled by configuring
an external bus under software control. Single chip mode allows the ST10F276 to start
execution out of the internal Flash program memory.
Any attempt to access a location in the external memory space in single chip mode results
in the hardware trap ILLBUS.