NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 7 Keyboard Interrupt (S08KBIV2)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 93
7.3.2 KBI Interrupt Pin Select Register (KBIPE)
7.3.3 KBI Interrupt Edge Select Register (KBIES)
7.4 Functional Description
This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was
designed to simplify the connection and use of row-column matrices of keyboard switches. However, these
inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from
stop or wait low-power modes. The KBI module allows up to eight pins to act as additional interrupt
sources.
Writing to the KBIPEn bits in the keyboard interrupt pin enable register (KBIPE) independently enables
or disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based
on the KBIMOD bit in the keyboard interrupt status and control register (KBISC). Edge sensitivity can be
software programmed to be either falling or rising; the level can be either low or high. The polarity of the
7 6 5 4 3 2 1 0
R
KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 7-3. KBI Interrupt Pin Select Register (KBIPE)
Table 7-3. KBIPE Register Field Descriptions
Field Description
7:0
KBIPE[7:0]
KBI Interrupt Pin Selects — Each of the KBIPEn bits enable the corresponding KBI interrupt pin.
0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.
7 6 5 4 3 2 1 0
R
KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0
W
Reset: 0 0 0 0 0 0 0 0
Figure 7-4. KBI Edge Select Register (KBIES)
Table 7-4. KBIxES Register Field Descriptions
Field Description
7:0
KBEDG[7:0]
KBI Edge Selects — Each of the KBEDGn bits serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pullup or pulldown device if enabled.
0 A pullup device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pulldown device is connected to the associated pin and detects rising edge/high level for interrupt
generation.