NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 8 Central Processor Unit (S08CPUV5)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 111
ROR opr8a
RORA
RORX
ROR oprx8 ,X
ROR ,X
ROR oprx8 ,SP
Rotate Right through
Carry

– –
  
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E66
dd
ff
ff
5
1
1
5
4
6
RSP Reset Stack Pointer
SP

0xFF
(High Byte Not Affected)
– – – – – –
INH 9C 1
RTI Return from Interrupt
SP

(SP) + 0x0001; Pull (CCR)
SP

(SP) + 0x0001; Pull (A)
SP

(SP) + 0x0001; Pull (X)
SP

(SP) + 0x0001; Pull (PCH)
SP

(SP) + 0x0001; Pull (PCL)
     
INH 80 9
RTS Return from Subroutine
SP

SP + 0x0001

Pull

PCH)
SP

SP + 0x0001; Pull (PCL)
– – – – – –
INH 81 6
SBC # opr8i
SBC opr8a
SBC opr16a
SBC oprx16 ,X
SBC oprx8 ,X
SBC ,X
SBC oprx16 ,SP
SBC oprx8 ,SP
Subtract with Carry A

(A) – (M) – (C)

– –
  
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A2
B2
C2
D2
E2
F2
9ED2
9EE2
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
SEC Set Carry Bit C

1
– – – – – 1
INH 99 1
SEI Set Interrupt Mask Bit I

1
– – 1 – – –
INH 9B 1
STA opr8a
STA opr16a
STA oprx16 ,X
STA oprx8 ,X
STA ,X
STA oprx16 ,SP
STA oprx8 ,SP
Store Accumulator in
Memory
M

(A)
0 – –
 
–
DIR
EXT
IX2
IX1
IX
SP2
SP1
B7
C7
D7
E7
F7
9ED7
9EE7
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
STHX opr8a
STHX opr16a
STHX oprx8 ,SP
Store H:X (Index Reg.) (M:M + 0x0001)

(H:X)
0 – –
 
–
DIR
EXT
SP1
35
96
9EFF
dd
hh ll
ff
4
5
5
STOP
Enable Interrupts:
Stop Processing
Refer to MCU
Documentation
I bit

0; Stop Processing
– – 0 – – –
INH 8E 2+
STX opr8a
STX opr16a
STX oprx16 ,X
STX oprx8 ,X
STX ,X
STX oprx16 ,SP
STX oprx8 ,SP
Store X (Low 8 Bits of
Index Register)
in Memory
M

(X)
0 – –
 
–
DIR
EXT
IX2
IX1
IX
SP2
SP1
BF
CF
DF
EF
FF
9EDF
9EEF
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
SUB # opr8i
SUB opr8a
SUB opr16a
SUB oprx16 ,X
SUB oprx8 ,X
SUB ,X
SUB oprx16 ,SP
SUB oprx8 ,SP
Subtract A

(A) – (M)

– –
  
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A0
B0
C0
D0
E0
F0
9ED0
9EE0
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
SWI Software Interrupt
PC

(PC) + 0x0001
Push (PCL); SP

(SP) – 0x0001
Push (PCH); SP

(SP) – 0x0001
Push (X); SP

(SP) – 0x0001
Push (A); SP

(SP) – 0x0001
Push (CCR); SP

(SP) – 0x0001
I

1;
PCH

Interrupt Vector High Byte
PCL

Interrupt Vector Low Byte
– – 1 – – –
INH 83 11
Table 8-2. HCS08 Instruction Set Summary (Sheet 6 of 7)
Source
Form
Operation Description
Effect
on CCR
Addre
ss
Mode
Op
co
de
Op
eran
d
Bu
s
C
ycl
es
1
V H I N Z C
b0 b7
C