NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 6 Parallel Input/Output Control
MC9S08QL8 MCU Series Reference Manual, Rev. 1
78 NXP Semiconductors
It is good programming practice to write to the port data register before changing the direction of a port
pin so it becomes an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
Figure 6-1. Parallel I/O Block Diagram
6.2 Pullup, Slew Rate, and Drive Strength
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pullups, slew rate, and drive
strength for the pins and may be used in conjunction with the peripheral functions on these pins.
6.2.1 Port Internal Pullup Enable
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTxPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
6.2.2
Port Slew Rate Enable
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
6.2.3
Port Drive Strength Select
An output pin can be configured for high output drive strength by setting the corresponding bit in the drive
strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinking
Q D
Q D
1
0
Port Read
PTxDDn
PTxDn
Output Enable
Output Data
Input Data
Synchronizer
Data
BUSCLK