NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 6 Parallel Input/Output Control
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 79
greater current. Even though every I/O pin can be selected as high drive, the user must ensure that the total
current source and sink limits for the MCU are not exceeded. Drive strength selection is intended to affect
the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive
a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of
this, the EMC emissions may be affected by enabling pins as high drive.
6.3 Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their pre-STOP
instruction state. CPU register status and the state of I/O registers must be saved in RAM before
the STOP instruction is executed to place the MCU in stop2 mode. Upon recovery from stop2
mode, before accessing any I/O, the user must examine the state of the PPDF bit in the SPMSC2
register. If the PPDF bit is 0, I/O must be initialized as if a power-on reset had occurred. If the PPDF
bit is 1, I/O register states must be restored from the values saved in RAM before the STOP
instruction was executed. Peripherals may require initialization or restoration to their pre-stop
condition. The user must then write a 1 to the PPDACK bit in the SPMSC2 register. Access to I/O
is again permitted in the user application program.
• In stop3 mode, all I/O is maintained because internal logic circuitry stays powered up. Upon
recovery, normal I/O function is available to the user.
6.4 Parallel I/O and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports. The data and
data direction registers are located in page zero of the memory map. The pull up, slew rate, drive strength,
and interrupt control registers are located in the high page section of the memory map.
Refer to tables in Chapter 4, Memory for the absolute address assignments for all parallel I/O and their pin
control registers. This section refers to registers and control bits only by their names. An NXP-provided
equate or header file is normally to translate these names into the appropriate absolute addresses.