NXP Semiconductors MC9S08QL4, Reference Manual

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Modulo Timer (S08MTIMV1)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 165
12.1.5 Block Diagram
The block diagram for the modulo timer module is shown Figure 12-1 .
Figure 12-1. Modulo Timer (MTIM) Block Diagram
12.2 External Signal Description
The MTIM includes one external signal, TCLK, used to input an external clock when selected as the
MTIM clock source. The signal properties of TCLK are shown in
Table 12-1 .
The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter
must be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency.
The TCLK pin can be muxed with a general-purpose port pin. See Chapter 2, Pins and Connections for the
pin location and priority of this function.
12.3 Register Definition
Figure 12-2 is a summary of MTIM registers.
Table 12-1. Signal Properties
Signal Function I/O
TCLK External clock source input into MTIM I
BUSCLK
TCLK SYNC
CLOCK
SOURCE
SELECT
PRESCALE
AND SELECT
DIVIDE BY
8-BIT COUNTER
(MTIMCNT)
8-BIT MODULO
(MTIMMOD)
8-BIT COMPARATOR
TRST
TSTP
CLKS PS
XCLK
TOIE
MTIM
INTERRU
PT
TOF