NXP Semiconductors MC9S08QL4, Reference Manual

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MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 7
5.8.9 System Power Management Status and Control 3 Register (SPMSC3) ...........................73
5.8.10 System Clock Gating Control 1 Register (SCGC1) ..........................................................74
5.8.11 System Clock Gating Control 2 Register (SCGC2) ..........................................................75
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ..........................................................................................................77
6.2 Pullup, Slew Rate, and Drive Strength ............................................................................................78
6.2.1 Port Internal Pullup Enable ...............................................................................................78
6.2.2 Port Slew Rate Enable ......................................................................................................78
6.2.3 Port Drive Strength Select ................................................................................................78
6.3 Pin Behavior in Stop Modes ............................................................................................................79
6.4 Parallel I/O and Pin Control Registers ............................................................................................79
6.4.1 Port A Registers ................................................................................................................80
6.4.2 Port B Registers ................................................................................................................82
6.4.3 Port C Registers ................................................................................................................85
Chapter 7
Keyboard Interrupt (S08KBIV2)
7.1 Introduction .....................................................................................................................................89
7.1.1 KBI Clock Gating .............................................................................................................89
7.1.2 Features .............................................................................................................................90
7.1.3 Modes of Operation ..........................................................................................................90
7.1.4 Block Diagram ..................................................................................................................90
7.2 External Signal Description ............................................................................................................91
7.3 Register Definition ..........................................................................................................................92
7.3.1 KBI Interrupt Status and Control Register (KBISC) ........................................................92
7.3.2 KBI Interrupt Pin Select Register (KBIPE) ......................................................................93
7.3.3 KBI Interrupt Edge Select Register (KBIES) ...................................................................93
7.4 Functional Description ....................................................................................................................93
7.4.1 Edge Only Sensitivity .......................................................................................................94
7.4.2 Edge and Level Sensitivity ...............................................................................................94
7.4.3 Pullup/Pulldown Resistors ................................................................................................94
7.4.4 Keyboard Interrupt Initialization ......................................................................................94
Chapter 8
Central Processor Unit (S08CPUV5)
8.1 Introduction .....................................................................................................................................95
8.1.1 Features .............................................................................................................................95
8.2 Programmer’s Model and CPU Registers .......................................................................................96
8.2.1 Accumulator (A) ...............................................................................................................96
8.2.2 Index Register (H:X) ........................................................................................................96
8.2.3 Stack Pointer (SP) .............................................................................................................97
8.2.4 Program Counter (PC) ......................................................................................................97
8.2.5 Condition Code Register (CCR) .......................................................................................97