NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 1 Device Overview
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 15
Table 1-2 provides the functional version of the on-chip modules.
1.3 System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs. The clock inputs to the modules indicate the clock(s) that are used to drive the module functions.
All memory mapped registers associated with the modules are clocked with BUSCLK.
Figure 1-2. System Clock Distribution Diagram
Table 1-2. Module Versions
Module Version
Analog Comparator (ACMPVLP) 1
Analog-to-Digital Converter (ADC12) 1
Central Processor Unit (CPU) 5
Internal Clock Source (ICS) 3
Keyboard Interrupt (KBI) 2
Low Power Oscillator (XOSCVLP) 1
Modulo Timer (MTIM) 1
Real-Time Counter (RTC) 1
Timer Pulse Width Modulator (TPM) 3
Serial Communications Interface (SCI) 4
TPM MTIM
BDC CPU ADC
3
FLASH
2
ICS
ICSOUT

2
BUSCLK
ICSLCLK
ICSIRCLK
COP
1
The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and
must not exceed one half of the bus clock frequency. It is XCLK in
Chapter 12,
Modulo Timer (S08MTIMV1) .
2
Flash has frequency requirements for program and erase operation. See
MC9S08QL8 Series
Data Sheet for details.
3
ADC has minimum and maximum frequency requirements. See Chapter 10,
Analog-to-Digital Converter (S08ADC12V1) and MC9S08QL8 Data Sheet for
details.
XOSCVLP
EXTAL
XTAL
FFCLK
1
ICSFFCLK
RTC
1 kHZ
LPO
TCLK
ICSERCLK

2
SYNC*
LPOCLK
OSCOUT
SCI