NXP Semiconductors MC9S08QL4, Reference Manual

Page: 58 / 240

Chapter 5 Resets, Interrupts, and General System Control
MC9S08QL8 MCU Series Reference Manual, Rev. 1
58 NXP Semiconductors
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT1 enabling the COP watchdog (see Section 5.8.4, System
Options Register 1 (SOPT1) for additional information). If the COP watchdog is not used in an application,
it can be disabled by clearing COPE. The COP counter is reset by writing any value to the address of SRS.
This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is
decoded and sends a reset signal to the COP counter.
The COPCLKS bit in SOPT2 (see Section 5.8.5, System Options Register 2 (SOPT2) for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1 kHz clock source. With each clock source, there is an associated short and long
time-out controlled by COPT in SOPT1.
Table 5-1 summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the 1 kHz clock source and the associated long
time-out (2
8
cycles).
Even if the application will use the reset default settings of COPE, COPCLKS, and COPT, the user must
write to the write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost. The initial writes to SOPT1
and SOPT2 will reset the COP counter.
The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
In background debug mode, the COP counter will not increment.
When the bus clock source is selected, the COP counter does not increment while the system is in stop
mode. The COP counter resumes as soon as the MCU exits stop mode.
Table 5-1. COP Configuration Options
Control Bits
Clock Source COP Overflow Count
COPCLKS COPT
0 0
~1 kHz
2
5
cycles (32 ms)
1
1
Values are shown in this column based on t
LPO
= 1 ms. See t
LPO
in the data sheet for the
tolerance of this value.
0 1
~1 kHz
2
8
cycles (256 ms)
1
1 0
Bus
2
13
cycles
1 1
Bus
2
18
cycles