NXP Semiconductors MC9S08QL4, Reference Manual

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Internal Clock Source (S08ICSV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 151
Figure 11-1. Internal Clock Source (ICS) Block Diagram
11.1.4 Modes of Operation
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.
11.1.4.1
FLL Engaged Interna
l (FEI)
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.
11.1.4.2
FLL Engaged External
(FEE)
In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an
external reference clock source. The BDC clock is supplied from the FLL.
11.1.4.3
FLL Bypassed Interna
l (FBI)
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied
from the FLL.
RDIV TRIM
/ 2
External Reference
IREFS
Clock
CLKS
n=0-10
/ 2
n
n=0-3
/ 2
n
Internal
Reference
Clock
BDIV
ICSLCLK
ICSOUT
ICSIRCLK
EREFS
RANGE
EREFSTEN
HGO
IREFSTEN
ICSERCLK
Internal Clock Source Block
ICSFFCLK
IRCLKEN
DCOOUT
DCOL
DCOM
DCOH
Filter
DRS
LP
FLL
DMX32 FTRIM
DRST IREFST CLKST OSCINIT
ICSDCLK
OSCOUT
ERCLKEN
STOP