NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 3 Modes of Operation
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 31
Stop3 recovery time = t
VRR
+ 1

sec + 1.4

sec Eqn. 3-4
When reset is used as the exit trigger, more time is required for the reset processing, so Equation 3-3
becomes
Stop3 recovery time = t
VRR
+ clock start up time + 162 ICSOUT cycles. Eqn. 3-5
Since ICSOUT defaults to FLL output running at 8.4 MHz during a reset, Equation 3-5 simplifies to
Stop3 recovery time = t
VRR
+ 1

sec + 19.3

sec. Eqn. 3-6
3.6.3 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in
Chapter 16, Development Support . If ENBDM is set when the CPU executes
a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation. If the user
attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available.
3.6.4 LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) the voltage
regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for
stop, the MCU will instead enter stop3.
3.6.5 Stop Modes in Low Power Run Mode
Stop2 mode cannot be entered from low power run mode. If the PPDC bit is set, then the LPR bit cannot
be set. Likewise, if the LPR bit is set, the PPDC bit cannot be set.
Stop3 mode can be entered from low power run mode by executing the STOP instruction while in low
power run. Exiting stop3 with a reset will put the device back into normal run mode. If LPWUI is clear,
interrupts will exit stop3 mode, return the device to low power run mode, and then service the interrupt. If
LPWUI is set, interrupts will exit stop3 mode, put the device into normal run mode, clear LPR and LPRS
bits, and then service the interrupt.
3.7 Mode Selection
Several control signals are used to determine the current operating mode of the device. Table 3-2 shows
the conditions for each of the device’s operating modes.