NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 2 Pins and Connections
MC9S08QL8 MCU Series Reference Manual, Rev. 1
22 NXP Semiconductors
NOTE
A resistive or capacitive load on the PTA4/ACMPO/BKGD/MS pin could
cause the MCU to enter active background mode on a POR if the pin voltage
rises slower than V
DD
.
The BKGD/MS pin is used primarily with BDC communications, and features a custom protocol that uses
16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock can run as fast
as the bus clock, so no significant capacitance must be connected to the BKGD/MS pin that could interfere
with background serial communications.
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play a minimal role in determining rise and fall
times on the BKGD/MS pin.
2.4.5 General-Purpose I/O (GPIO) and Peripheral Ports
The MC9S08QL8 series of MCUs support up to 16 general-purpose I/O pins, 1 input-only pin, and 1
output-only pin, which are shared with on-chip peripheral functions (timer, ADC, ACMP, etc.). The GPIO
output-only (PTA4/ACMPO/BKGD/MS) and input-only (PTA5/IRQ/TCLK/RESET) pins are
bi-directional when configured as BKGD and RESET, respectively.
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pullup device.
PTA5 is a special I/O pin. When the PTA5/IRQ/TCLK/RESET pin is configured as PTA5 input with the
pullup enabled, the voltage observed on the pin will not be pulled to V
DD
. However, the internal voltage
on the PTA5 node will be at V
DD
.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see
Chapter 6, Parallel Input/Output Control .
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program must enable on-chip pullup devices or
change the direction of unused or non-bonded pins to outputs so they do not
float.
When using the 16-pin device, the user must either enable on-chip pullup
devices or change the direction of non-bonded PTC3–PTC0 pins to outputs
so the pins do not float.