NXP Semiconductors MC9S08QL4, Reference Manual

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Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 217
15.4 Functional Description
All TPM functions are associated with a central 16-bit counter that allows flexible selection of the clock
and prescale factor. There is also a 16-bit modulo register associated with this counter.
The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM
(CPWMS=1) or general purpose timing functions (CPWMS=0) where each channel can independently be
configured to operate in input capture, output compare, or edge-aligned PWM mode. The CPWMS control
bit is located in the TPM status and control register because it affects all channels within the TPM and
influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down mode
rather than the up-counting mode used for general purpose timer functions.)
The following sections describe TPM counter and each of the timer operating modes (input capture, output
compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt
activity depend upon the operating mode, these topics are covered in the associated mode explanation
sections.
15.4.1 Counter
All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section
discusses selection of the clock, end-of-count overflow, up-counting vs. up/down counting, and manual
counter reset.
15.4.1.1 Counter Clock Source
The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPMxSC) disables the TPM
counter or selects one of three clock sources to TPM counter (
Table 15-6 ). After any MCU reset, CLKSB
and CLKSA are cleared so no clock is selected and the TPM counter is disabled (TPM is in a very low
power state). You can read or write these control bits at any time. Disabling the TPM counter by writing
00 to CLKSB:CLKSA bits, does not affect the values in the TPM counter or other registers.
The fixed frequency clock is an alternative clock source for the TPM counter that allows the selection of
a clock other than the bus clock or external clock. This clock input is defined by chip integration. You can
refer chip specific documentation for further information. Due to TPM hardware implementation
limitations, the frequency of the fixed frequency clock must not exceed the bus clock frequency. The fixed
frequency clock has no limitations for low frequency operation.
The external clock passes through a synchronizer clocked by the bus clock to assure that counter
transitions are properly aligned to bus clock transitions.Therefore, in order to meet Nyquist criteria
considering also jitter, the frequency of the external clock source must not exceed 1/4 of the bus clock
frequency.
When the external clock source is shared with a TPM channel pin, this pin must not be used in input
capture mode. However, this channel can be used in output compare mode with ELSnB:ELSnA = 0:0 for
software timing functions. In this case, the channel output is disabled, but the channel match events
continue to set the appropriate flag.