NXP Semiconductors MC9S08QL4, Reference Manual

Page: 75 / 240

Chapter 5 Resets, Interrupts, and General System Control
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 75
5.8.11 System Clock Gating Control 2 Register (SCGC2)
This high page register contains control bits to enable or disable the bus clock to the Flash, IRQ, KBI,
ACMP and RTC modules. Gating off the clocks to unused peripherals is used to reduce the MCU’s run
and wait currents. See
Section 5.7, Peripheral Clock Gating for more information.
NOTE
User software must disable the peripheral before disabling the clocks to the
peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers must be re-initialized by user software.
7 6 5 4 3 2 1 0
R 1
FLS IRQ KBI ACMP RTC
1 1
W — — —
Reset: 1 1 1 1 1 1 1 1
= Unimplemented or Reserved
Figure 5-13. System Clock Gating Control 2 Register (SCGC2)
Table 5-15. SCGC2 Register Field Descriptions
Field Description
6
FLS
Flash Register Clock Gate Control — This bit controls the bus clock gate to the Flash module.
0 Bus clock to the Flash module is disabled.
1 Bus clock to the Flash module is enabled.
5
IRQ
IRQ Clock Gate Control — This bit controls the bus clock gate to the IRQ module.
0 Bus clock to the IRQ module is disabled.
1 Bus clock to the IRQ module is enabled.
4
KBI
KBI Clock Gate Control — This bit controls the clock gate to the KBI module.
0 Bus clock to the KBI module is disabled.
1 Bus clock to the KBI module is enabled.
3
ACMP
ACMP Clock Gate Control — This bit controls the clock gate to both of the ACMP modules.
0 Bus clock to the ACMP modules is disabled.
1 Bus clock to the ACMP modules is enabled.
2
RTC
RTC Clock Gate Control — This bit controls the bus clock gate to the RTC module. Only the bus clock is gated,
the ICSERCLK and LPOCLK are still available to the RTC.
0 Bus clock to the RTC module is disabled.
1 Bus clock to the RTC module is enabled.