NXP Semiconductors MC9S08QL4 Reference Manual Download

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Chapter 8 Central Processor Unit (S08CPUV5)

MC9S08QL8 MCU Series Reference Manual, Rev. 1

114

NXP Semiconductors

Bit-Manipulation

Branch

Read-Modify-Write

Control

Register/Memory

9E60

NEG

SP1

9ED0

SUB

SP2

9EE0

SUB

SP1

9E61

CBEQ

SP1

9ED1

CMP

SP2

9EE1

CMP

SP1

9ED2

SBC

SP2

9EE2

SBC

SP1

9E63

COM

SP1

9ED3

CPX

SP2

9EE3

CPX

SP1

9EF3

CPHX

SP1

9E64

LSR

SP1

9ED4

AND

SP2

9EE4

AND

SP1

9ED5

BIT

SP2

9EE5

BIT

SP1

9E66

ROR

SP1

9ED6

LDA

SP2

9EE6

LDA

SP1

9E67

ASR

SP1

9ED7

STA

SP2

9EE7

STA

SP1

9E68

LSL

SP1

9ED8

EOR

SP2

9EE8

EOR

SP1

9E69

ROL

SP1

9ED9

ADC

SP2

9EE9

ADC

SP1

9E6A

DEC

SP1

9EDA

ORA

SP2

9EEA

ORA

SP1

9E6B

DBNZ

SP1

9EDB

ADD

SP2

9EEB

ADD

SP1

9E6C

INC

SP1

9E6D

TST

SP1

9EAE

LDHX

9EBE

LDHX

IX2

9ECE

LDHX

IX1

9EDE

LDX

SP2

9EEE

LDX

SP1

9EFE

LDHX

SP1

9E6F

CLR

SP1

9EDF

STX

SP2

9EEF

STX

SP1

9EFF

STHX

SP1

INH

Inherent

REL

Relative

SP1

Stack Pointer, 8-Bit Offset

IMM

Immediate

Indexed, No Offset

SP2

Stack Pointer, 16-Bit Offset

DIR

Direct

IX1

Indexed, 8-Bit Offset

IX+

Indexed, No Offset with

EXT

Extended

IX2

Indexed, 16-Bit Offset

Post Increment

DIR to DIR

IMD

IMM to DIR

IX1+

Indexed, 1-Byte Offset with

IX+D

IX+ to DIR

DIX+

DIR to IX+

Post Increment

Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)

Prebyte (9E) and Opcode in

Hexadecimal

Number of Bytes

9E60

NEG

SP1

HCS08 Cycles

Instruction Mnemonic

Addressing Mode

Table 8-3. Opcode Map (Sheet 2 of 2)

Summary of Contents for MC9S08QL4

Page 1: ...MC9S08QL8 MCU Series Reference Manual Rev 1 NXP Semiconductors 1 MC9S08QL8 MCU Series Reference Manual Covers MC9S08QL8 MC9S08QL4 MC9S08QL8RM Rev 1 07 2018...

Page 2: ...rrent Your printed copy may be an earlier revision To verify you have the latest information available refer to http nxp com The following revision history table summarizes changes contained in this d...

Page 3: ...6 Parallel Input Output Control 77 Chapter 7 Keyboard Interrupt S08KBIV2 89 Chapter 8 Central Processor Unit S08CPUV5 95 Chapter 9 Analog Comparator S08ACMPVLPV1 115 Chapter 10 Analog to Digital Conve...

Page 4: ...MC9S08QL8 MCU Series Reference Manual Rev 1 4 NXP Semiconductors...

Page 5: ...in 21 2 4 4 Background Mode Select BKGD MS 21 2 4 5 General Purpose I O GPIO and Peripheral Ports 22 Chapter 3 Modes of Operation 3 1 Introduction 25 3 2 Features 25 3 3 Run Mode 25 3 3 1 Low Power Ru...

Page 6: ...res 57 5 3 MCU Reset 57 5 4 Computer Operating Properly COP Watchdog 58 5 5 Interrupts 59 5 5 1 Interrupt Stack Frame 60 5 5 2 External Interrupt Request IRQ Pin 60 5 5 3 Interrupt Vectors Sources and...

Page 7: ...ers 85 Chapter 7 Keyboard Interrupt S08KBIV2 7 1 Introduction 89 7 1 1 KBI Clock Gating 89 7 1 2 Features 90 7 1 3 Modes of Operation 90 7 1 4 Block Diagram 90 7 2 External Signal Description 91 7 3 R...

Page 8: ...onfiguration Information 115 9 1 2 ACMP TPM Configuration Information 115 9 1 3 ACMP Clock Gating 115 9 1 4 Stop1 Not Available 115 9 1 5 Features 116 9 1 6 Modes of Operation 116 9 1 7 Block Diagram...

Page 9: ...6 MCU Wait Mode Operation 140 10 4 7 MCU Stop3 Mode Operation 140 10 4 8 MCU Stop2 Mode Operation 141 10 5 Initialization Information 141 10 5 1 ADC Module Initialization Example 141 10 6 Application...

Page 10: ...Register MTIMMOD 169 12 4 Functional Description 170 12 4 1 MTIM Operation Example 171 Chapter 13 Real Time Counter S08RTCV1 13 1 Introduction 173 13 1 1 ADC Hardware Trigger 173 13 1 2 RTC Clock Sou...

Page 11: ...th Modulator S08TPMV3 15 1 Introduction 201 15 1 1 ACMP TPM Configuration Information 201 15 1 2 TPM External Clock 201 15 1 3 TPM Pin Repositioning 201 15 1 4 TPM Clock Gating 201 15 1 5 TPMV3 Differ...

Page 12: ...6 1 1 Forcing Active Background 225 16 1 2 Module Configuration 225 16 1 3 Features 226 16 2 Background Debug Controller BDC 226 16 2 1 BKGD Pin Description 227 16 2 2 Communication Details 227 16 2 3...

Page 13: ...types and package types 1 1 Devices in the MC9S08QL8 Series Table 1 1 summarizes the feature set available in the MC9S08QL8 series of MCUs t Table 1 1 MC9S08QL8 Series Features by MCU and Package Fea...

Page 14: ...2 KBIP6 ADP6 VOLTAGE REGULATOR PORT A PTA1 KBIP1 ADP1 ACMP ANALOG COMPARATOR ACMP LOW POWER OSCILLATOR 20 MHz INTERNAL CLOCK SOURCE ICS 31 25 kHz to 38 4 kHz 1 MHz to 16 MHz XOSC VSS VDD ANALOG TO DIG...

Page 15: ...entral Processor Unit CPU 5 Internal Clock Source ICS 3 Keyboard Interrupt KBI 2 Low Power Oscillator XOSCVLP 1 Modulo Timer MTIM 1 Real Time Counter RTC 1 Timer Pulse Width Modulator TPM 3 Serial Com...

Page 16: ...dules ICSIRCLK This is the internal reference clock and can be selected as the real time counter clock source Chapter 11 Internal Clock Source S08ICSV3 explains the ICSIRCLK in more detail See Chapter...

Page 17: ...2 2 shows the pin assignments in the packages for the MC9S08QL8 series devices Figure 2 1 MC9S08QL8 Series in 20 Pin TSSOP Package 1 2 3 4 5 6 7 8 9 10 11 13 14 PTC2 PTB4 PTC3 PTC0 PTB3 KBIP7 ADP7 PTB...

Page 18: ...8QL8 Series in 16 Pin TSSOP Packages 1 2 3 4 5 6 7 8 9 10 11 13 14 PTB4 PTB3 KBIP7 ADP7 PTB2 KBIP6 ADP6 PTB1 KBIP5 TxD ADP5 PTB0 KBIP4 RxD ADP4 PTA2 KBIP2 ADP2 PTA3 KBIP3 ADP3 PTA1 KBIP1 ADP1 ACMP PTA...

Page 19: ...ATOR OPTIONAL EMC PROTECTION VDD 4 7 k 10 k 0 1 F XTAL EXTAL NOTES 1 VDDA VREFH and VSSA VREFL are tired with VDD and VSS respectively 2 RESET pin can only be used to reset into user mode you can not...

Page 20: ...ule The oscillator can be configured to run in stop2 or stop3 modes For more information on the ICS see Chapter 11 Internal Clock Source S08ICSV3 The oscillator XOSCVLP in this MCU is a Pierce oscilla...

Page 21: ...must not be driven above VDD NOTE The voltage on the internally pulled up RESET pin when measured will be below VDD The internal gates connected to this pin are pulled to VDD If the RESET pin is requi...

Page 22: ...TA5 IRQ TCLK RESET pins are bi directional when configured as BKGD and RESET respectively When a port pin is configured as a general purpose output or a peripheral uses the port pin as an output softw...

Page 23: ...VDD 4 4 VSS 5 5 PTB7 EXTAL 6 6 PTB6 XTAL 7 7 PTB5 TPMCH01 1 TPMCH0 pin can be repositioned at PTB5 using TPMCH0PS in SOPT2 default reset location is PTA0 8 8 PTB4 9 PTC3 10 PTC2 11 PTC1 12 PTC0 13 9 P...

Page 24: ...Chapter 2 Pins and Connections MC9S08QL8 MCU Series Reference Manual Rev 1 24 NXP Semiconductors...

Page 25: ...tor is in standby Stop modes System clocks are stopped and voltage regulator is in standby Stop3 All internal circuits are powered for fast recovery Stop2 Partial power down of internal circuits RAM c...

Page 26: ...ting the LPWUI bit in the SPMSC2 register The ICS can then be set for full speed immediately in the interrupt service routine If the LPWUI bit is clear interrupts will be serviced in low power run mod...

Page 27: ...For additional information about the active background mode refer to the Chapter 16 Development Support 3 5 Wait Mode Wait mode is entered by executing a WAIT instruction Upon execution of the WAIT in...

Page 28: ...egulator is in standby In stop2 the voltage regulator is in partial powerdown The ICS module can be configured to leave the reference clocks running See Chapter 11 Internal Clock Source S08ICSV3 for m...

Page 29: ...point The CPU takes the reset vector In addition to the above upon waking from stop2 the PPDF bit in SPMSC2 is set This flag is used to direct user code to go to a stop2 recovery routine PPDF remains...

Page 30: ...the internal interrupt sources results in the MCU taking the appropriate interrupt vector 3 6 2 1 Stop3 Mode Recovery Time The stop3 recovery time is defined as the interval from the exit trigger to t...

Page 31: ...that the MCU is in either stop or wait mode The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set After entering background debug mode a...

Page 32: ...n LPWAIT mode Assumes WAIT instruction executed 0 0 x 1 0 CPU clock is off peripheral clocks at low speed ICS in FBELP mode off standby 1 0 STOP3 Assumes STOPE bit is set and STOP instruction executed...

Page 33: ...re 3 1 Transition From To Trigger 1 RUN LPRUN Configure settings shown in Table 3 1 switch LPR 1 last LPRUN RUN Clear LPR Interrupt when LPWUI 1 2 RUN STOP2 Pre configure settings shown in Table 3 1 i...

Page 34: ...Wait LPRun CPU Off Standby Standby On RAM Standby Standby Standby On Flash Off Standby Standby On Port I O Registers Off Standby Standby On ADC Off Optionally On1 1 Requires the asynchronous ADC clock...

Page 35: ...espectively 5 IRCLKEN and IREFSTEN set in ICSC1 else in standby 6 ICS must be configured for FBELP bus frequency limited to 125 kHz in LPRUN or LPWAIT 7 If LVDSE is set when entering stop2 the MCU wil...

Page 36: ...Chapter 3 Modes of Operation MC9S08QL8 MCU Series Reference Manual Rev 1 36 NXP Semiconductors...

Page 37: ...Interrupt Vector Assignments Table 4 1 shows address assignments for reset and interrupt vectors The vector names shown in this table are the labels used in the NXP Semiconductors provided equate fil...

Page 38: ...rsion Vadc 0xFFDA 0xFFDB KBI Interrupt Vkeyboard 0xFFDC 0xFFDD Reserved 0xFFDE 0xFFDF SCI Transmit Vscitx 0xFFE0 0xFFE1 SCI Receive Vscirx 0xFFE2 0xFFE3 SCI Error Vscierr 0xFFE4 0xFFE5 Reserved 0xFFE6...

Page 39: ...ations are flash memory they must be erased and programmed like other flash memory locations Direct page registers can be accessed with efficient direct addressing mode instructions Bit manipulation i...

Page 40: ...0 ADCSC1 COCO AIEN ADCO ADCH 0x0011 ADCSC2 ADACT ADTRG ACFE ACFGT 0 0 R R 0x0012 ADCRH 0 0 0 0 ADR11 ADR10 ADR9 ADR8 0x0013 ADCRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0x0014 ADCCVH 0 0 0 0 ADCV11 A...

Page 41: ...7 6 5 4 3 2 1 Bit 0 0x0045 TPMC0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0046 TPMC0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0047 TPMC0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0048 0x005F Reserved Table 4 3 High Page...

Page 42: ...the factory trim 0x1810 0x181F Reserved 0x1820 FCDIV DIVLD PRDIV8 DIV 0x1821 FOPT KEYEN FNORED 0 0 0 0 SEC01 SEC00 0x1822 Reserved 0x1823 FCNFG 0 0 KEYACC 0 0 0 0 0 0x1824 FPROT FPS FPDIS 0x1825 FSTAT...

Page 43: ...power on the contents of RAM are uninitialized RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention VRAM For compatibility with...

Page 44: ...le block protection Security feature for flash and RAM Auto power down for low frequency read accesses 4 5 2 Program and Erase Times Before any program or erase command can be accepted the flash clock...

Page 45: ...h 2 Write the command code for the desired command to FCMD The five valid commands are blank check 0x05 byte program 0x20 burst program 0x25 page erase 0x40 and mass erase 0x41 The command code is lat...

Page 46: ...When a burst program command is issued the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met The next burst program comman...

Page 47: ...he standard time instead of the burst time This is because the high voltage to the array must be disabled and then enabled again If a new burst command has not been queued before the current command c...

Page 48: ...ound debug command while the MCU is secured The background debug controller can only do blank check and mass erase commands when the MCU is secure Writing 0 to FCBEF to cancel a partial command 4 5 6...

Page 49: ...ors 0xFFC0 0xFFFD are redirected to the locations 0xFDC0 0xFDFD For instance if a TPM overflow interrupt is taken the values in the locations 0xFDF0 FDF1 are used for the vector instead of the values...

Page 50: ...ches the key stored in the flash locations SEC01 SEC00 are automatically changed to 1 0 and security will be disengaged until the next reset The security key can be written only from secure memory eit...

Page 51: ...ield Descriptions Field Description 7 DIVLD Divisor Loaded Status Flag When set this read only status flag indicates that the FCDIV register has been written since reset Reset clears this bit and the...

Page 52: ...this bit is 0 the backdoor key mechanism cannot be used to disengage security The backdoor key mechanism is accessible only from user secured firmware BDM commands cannot be used to write key compari...

Page 53: ...entry or a successful blank check of flash SEC01 SEC00 Description 0 0 secure 0 1 secure 1 0 unsecured 1 1 secure 7 6 5 4 3 2 1 0 R 0 0 KEYACC 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reser...

Page 54: ...cates that the command buffer is empty so that a new command sequence can be executed when performing burst programming The FCBEF bit is cleared by writing a 1 to it or when a burst program command is...

Page 55: ...ered access errors see Section 4 5 5 Access Errors FACCERR is cleared by writing a 1 to FACCERR Writing a 0 to FACCERR has no meaning or effect 0 No access error 1 An access error has occurred 2 FBLAN...

Page 56: ...Chapter 4 Memory MC9S08QL8 MCU Series Reference Manual Rev 1 56 NXP Semiconductors...

Page 57: ...rrupt vector for most modules reduces polling overhead see Table 5 2 5 3 MCU Reset Resetting the MCU provides a way to start processing from a known set of initial conditions During reset most control...

Page 58: ...er the bus clock or an internal 1 kHz clock source With each clock source there is an associated short and long time out controlled by COPT in SOPT1 Table 5 1 summaries the control functions of the CO...

Page 59: ...CPU registers on the stack Setting the I bit in the CCR to mask further interrupts Fetching the interrupt vector for the highest priority interrupt that is currently pending Filling the instruction qu...

Page 60: ...before returning from the ISR Typically the flag is cleared at the beginning of the ISR so that if another interrupt is generated by this same source it will be registered so it can be serviced after...

Page 61: ...ls In the edge and level detection mode the IRQF status flag becomes set when an edge is detected when the IRQ pin changes from the deasserted to the asserted level but the flag is continuously set an...

Page 62: ...SCI TDRE TC TIE TCIE SCI transmit 15 0xFFE0 0xFFE1 Vscirx SCI IDLE RDRF LBKDIF RXEDGIF ILIE RIE LBKDIE RXEDGIE SCI receive 14 0xFFE2 0xFFE3 Vscierr SCI OR NF FE PF ORIE NFIE FEIE PFIE SCI error 13 0xF...

Page 63: ...risen above the low voltage detection threshold The LVD bit in the SRS register is set following either an LVD reset or POR 5 6 3 Low Voltage Detection LVD Interrupt Operation When a low voltage cond...

Page 64: ...space are related to reset and interrupt systems Refer to Table 4 2 and Table 4 3 in Chapter 4 Memory for the absolute address assignments for all registers This section refers to registers and contr...

Page 65: ...enables the IRQ pin function When this bit is set the IRQ pin can be used as an interrupt request 0 IRQ pin function is disabled 1 IRQ pin function is enabled 3 IRQF IRQ Flag This read only status bit...

Page 66: ...s ramping up at the time the low voltage reset LVD status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold 0 Reset not caused by POR 1 POR caus...

Page 67: ...Reserved 1 BDFR is writable only through serial background debug commands not from user programs Figure 5 4 System Background Debug Force Reset Register SBDFR Table 5 5 SBDFR Register Field Descriptio...

Page 68: ...rite once bit is used to enable stop mode If stop mode is disabled and a user program attempts to execute a STOP instruction an illegal opcode reset is forced 0 Stop mode disabled 1 Stop mode enabled...

Page 69: ...e 5 7 SOPT2 Register Field Descriptions Field Description 7 COPCLKS COP Watchdog Clock Select This write once bit selects the clock source of the COP watchdog 0 Internal 1 kHz clock is source to COP 1...

Page 70: ...5 8 SDIDH Register Field Descriptions Field Description 7 4 Reserved Bits 7 4 are reserved Reading these bits will result in an indeterminate value writes have no effect 3 0 ID 11 8 Part Identificati...

Page 71: ...VDACK Low Voltage Detect Acknowledge This write only bit is used to acknowledge low voltage detection errors write 1 to clear LVDF Reads always return 0 5 LVDIE Low Voltage Detect Interrupt Enable Thi...

Page 72: ...terrupt occurs 0 Low power run and wait modes are disabled 1 Low power run and wait modes are enabled 6 LPRS Low Power Regulator Status This read only status bit indicates that the voltage regulator h...

Page 73: ...Management Status and Control 3 Register SPMSC3 Table 5 12 SPMSC3 Register Field Descriptions Field Description 7 LVWF Low Voltage Warning Flag The LVWF bit indicates the low voltage warning status 0...

Page 74: ...6 5 4 3 2 1 0 R MTIM 1 TPM ADC 1 1 1 SCI W Reset 1 1 1 1 1 1 1 1 Figure 5 12 System Clock Gating Control 1 Register SCGC1 Table 5 14 SCGC1 Register Field Descriptions Field Description 7 MTIM MTIM Clo...

Page 75: ...able 5 15 SCGC2 Register Field Descriptions Field Description 6 FLS Flash Register Clock Gate Control This bit controls the bus clock gate to the Flash module 0 Bus clock to the Flash module is disabl...

Page 76: ...Chapter 5 Resets Interrupts and General System Control MC9S08QL8 MCU Series Reference Manual Rev 1 76 NXP Semiconductors...

Page 77: ...pplication program must either enable on chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float 6 1 Port Data and Data Direction Reading and writing of par...

Page 78: ...ach port pin by setting the corresponding bit in the pullup enable register PTxPEn The pullup device is disabled if the pin is configured as an output by the parallel I O control logic or any shared p...

Page 79: ...O the user must examine the state of the PPDF bit in the SPMSC2 register If the PPDF bit is 0 I O must be initialized as if a power on reset had occurred If the PPDF bit is 1 I O register states must...

Page 80: ...n bit PTADD4 Figure 6 2 Port A Data Register PTAD Table 6 1 PTAD Register Field Descriptions Field Description 5 0 PTAD 5 0 Port A Data Register Bits For port A pins that are inputs reads return the l...

Page 81: ...or port A pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup pulldown device disabled for port A bit n 1 Internal pullup pulldow...

Page 82: ...W Reset 0 0 0 0 0 0 0 0 Figure 6 6 Drive Strength Selection for Port A Register PTADS Table 6 5 PTADS Register Field Descriptions Field Description 4 0 PTADS 4 0 Output Drive Strength Selection for P...

Page 83: ...o all bits of this register For port B pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTBD to all 0s but these 0s are not driven out the corre...

Page 84: ...port B pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup pulldown device disabled for port B bit n 1 Internal pullup pulldown...

Page 85: ...igure 6 11 Drive Strength Selection for Port B Register PTBDS Table 6 10 PTBDS Register Field Descriptions Field Description 7 0 PTBDS 7 0 Output Drive Strength Selection for Port B Bits Each of these...

Page 86: ...s outputs the logic level is driven out of the corresponding MCU pin Reset forces PTCD to all 0s but these 0s are not driven out of the corresponding pins because reset also configures all port pins a...

Page 87: ...For port C pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for port C bit n 1 Internal pullup device enabled...

Page 88: ...Strength Selection for Port C Register PTCDS Table 6 15 PTCDS Register Field Descriptions Field Description 3 0 PTCDS 3 0 Output Drive Strength Selection for Port C Bits Each of these control bits se...

Page 89: ...ght independently enabled external interrupt sources 7 1 1 KBI Clock Gating The bus clock to the KBI can be gated on and off using the KBI bit in SCGC2 This bit is set after any reset which enables th...

Page 90: ...I continues to operate in wait mode if enabled before executing the WAIT instruction Therefore an enabled KBI pin KBPEx 1 can be used to bring the MCU out of wait mode if the KBI interrupt is enabled...

Page 91: ...ng edge and low level interrupt requests The KBI input pins can also be used to detect either rising edges or both rising edge and high level interrupt requests Table 7 1 KBI Pin Mapping Port pin PTB3...

Page 92: ...KBIE KBIMOD W KBACK Reset 0 0 0 0 0 0 0 0 Figure 7 2 KBI Interrupt Status and Control Register KBISC Table 7 2 KBISC Register Field Descriptions Field Description 3 KBF KBI Interrupt Flag KBF indicate...

Page 93: ...e sensitivity can be software programmed to be either falling or rising the level can be either low or high The polarity of the 7 6 5 4 3 2 1 0 R KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE...

Page 94: ...et an interrupt request will be presented to the CPU Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC provided all enabled port inputs are at their deasserted levels KBF will remain se...

Page 95: ...ingle 64 Kbyte address space 16 bit stack pointer any size stack anywhere in 64 KB CPU address space 16 bit index register H X with powerful indexed addressing modes 8 bit accumulator A Many instructi...

Page 96: ...8 bit registers H and X which often work together as a 16 bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address All indexed addressing mode instructi...

Page 97: ...bility with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low order half of the stack pointer 8 2 4 Program Counter PC The program counter is a 16 bit registe...

Page 98: ...n of the interrupt service routine is executed Interrupts are not recognized at the instruction boundary after any instruction that clears I CLI or TAP This ensures that the next instruction after a C...

Page 99: ...if any are located within CPU registers so the CPU does not need to access memory to get any operands 8 3 2 Relative Addressing Mode REL Relative addressing mode is used to specify the destination lo...

Page 100: ...is only used for MOV and CBEQ instructions 8 3 6 3 Indexed 8 Bit Offset IX1 This variation of indexed addressing uses the 16 bit value in the H X index register pair plus an unsigned 8 bit offset incl...

Page 101: ...n is no longer asserted At the conclusion of a reset event the CPU performs a 6 cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for exe...

Page 102: ...o the MCU through the background debug interface while the CPU is in wait mode CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be proces...

Page 103: ...ng user instructions and enter the active background mode The only way to resume execution of the user program is through reset or by a host debug system issuing a GO TRACE1 or TAGGO serial command th...

Page 104: ...X Index register lower order least significant 8 bits PC Program counter PCH Program counter higher order most significant 8 bits PCL Program counter lower order least significant 8 bits SP Stack poi...

Page 105: ...es to a single integer in the range 0 7 opr8i Any label or expression that evaluates to an 8 bit immediate value opr16i Any label or expression that evaluates to a 16 bit immediate value opr8a Any lab...

Page 106: ...2 3 4 4 3 3 5 4 ADD opr8i ADD opr8a ADD opr16a ADD oprx16 X ADD oprx8 X ADD X ADD oprx16 SP ADD oprx8 SP Add without Carry A A M IMM DIR EXT IX2 IX1 IX SP2 SP1 AB BB CB DB EB FB 9EDB 9EEB ii dd hh ll...

Page 107: ...Branch if IRQ Pin High Branch if IRQ pin 1 REL 2F rr 3 BIL rel Branch if IRQ Pin Low Branch if IRQ pin 0 REL 2E rr 3 BIT opr8i BIT opr8a BIT opr16a BIT oprx16 X BIT oprx8 X BIT X BIT oprx16 SP BIT op...

Page 108: ...M Branch if A M Branch if A M DIR IMM IMM IX1 IX SP1 31 41 51 61 71 9E61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 CLC Clear Carry Bit C 0 0 INH 98 1 CLI Clear Interrupt Mask Bit I 0 0 INH 9A 1 CLR...

Page 109: ...A A M 0 IMM DIR EXT IX2 IX1 IX SP2 SP1 A8 B8 C8 D8 E8 F8 9ED8 9EE8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 INC opr8a INCA INCX INC oprx8 X INC X INC oprx8 SP Increment M M 0x01 A A 0x01 X X 0x01...

Page 110: ...0x00 X M M 0x00 M M M 0x00 M M M 0x00 M DIR INH INH IX1 IX SP1 30 40 50 60 70 9E60 dd ff ff 5 1 1 5 4 6 NOP No Operation Uses 1 Bus Cycle INH 9D 1 NSA Nibble Swap Accumulator A A 3 0 A 7 4 INH 62 1 O...

Page 111: ...mory M A 0 DIR EXT IX2 IX1 IX SP2 SP1 B7 C7 D7 E7 F7 9ED7 9EE7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 STHX opr8a STHX opr16a STHX oprx8 SP Store H X Index Reg M M 0x0001 H X 0 DIR EXT SP1 35 96 9EFF...

Page 112: ...A 0x00 X 0x00 M 0x00 M 0x00 M 0x00 0 DIR INH INH IX1 IX SP1 3D 4D 5D 6D 7D 9E6D dd ff ff 4 1 1 4 3 5 TSX Transfer SP to Index Reg H X SP 0x0001 INH 95 2 TXA Transfer X Index Reg Low to Accumulator A...

Page 113: ...8 5 BRSET4 3 DIR 18 5 BSET4 2 DIR 28 3 BHCC 2 REL 38 5 LSL 2 DIR 48 1 LSLA 1 INH 58 1 LSLX 1 INH 68 5 LSL 2 IX1 78 4 LSL 1 IX 88 3 PULX 1 INH 98 1 CLC 1 INH A8 2 EOR 2 IMM B8 3 EOR 2 DIR C8 4 EOR 3 EX...

Page 114: ...E6A 6 DEC 3 SP1 9EDA 5 ORA 4 SP2 9EEA 4 ORA 3 SP1 9E6B 8 DBNZ 4 SP1 9EDB 5 ADD 4 SP2 9EEB 4 ADD 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 LDHX 2 IX 9EBE 6 LDHX 4 IX2 9ECE 5 LDHX 3 IX1 9EDE 5 LDX...

Page 115: ...Control 1 Register SPMSC1 for value of bandgap voltage reference see the data sheet BKGDPE bit in SOPT1 register is set following any reset of the MCU and must be cleared to use the PTA4 ACMPO BKGD MS...

Page 116: ...e in stop3 mode and compare operation remains active If ACOPE is enabled comparator output operates in the normal operating mode and comparator output is placed onto the external pin The MCU is brough...

Page 117: ...CU documentation to determine what functions are shared with these analog inputs As shown in the block diagram the ACMP pin is connected to the comparator non inverting input if ACBGS is equal to logi...

Page 118: ...Comparator enabled 6 ACBGS Analog Comparator Bandgap Select The ACBGS bit selects the internal bandgap as the comparator reference 0 External pin ACMP selected as comparator non inverting input 1 Int...

Page 119: ...parator S08ACMPVLPV1 MC9S08QL8 MCU Series Reference Manual Rev 1 NXP Semiconductors 119 ACIE bit or the ACF bit The ACIE bit is cleared by writing a logic zero and the ACF bit is cleared by writing a...

Page 120: ...Analog Comparator S08ACMPVLPV1 MC9S08QL8 MCU Series Reference Manual Rev 1 120 NXP Semiconductors...

Page 121: ...g Supply and Voltage Reference Connections The MC9S08QL8 series VDDA VREFH and VSSA VREFL pins are double bonded to VDD and VSS in the 20 pin and 16 pin packages 10 1 2 2 Configurations for Stop and L...

Page 122: ...o trigger the ADC The RTC can be clocked by either ICSIRCLK OSCOUT or LPO The period of the RTC is determined by the input clock frequency and the RTC configuration bits When the ADC hardware trigger...

Page 123: ...of the temperature sensor Temp 25 VTEMP VTEMP25 m Eqn 10 1 where VTEMP is the voltage of the temperature sensor channel at the ambient temperature VTEMP25 is the voltage of the temperature sensor cha...

Page 124: ...omatic return to idle after single conversion Configurable sample time and conversion speed power Conversion complete flag and interrupt Input clock selectable from up to four sources Operation in wai...

Page 125: ...tion AD27 AD0 Analog Channel inputs VREFH High reference voltage VREFL Low reference voltage VDDA Analog power supply VSSA Analog ground AD0 AD27 VREFH VREFL ADVIN ADCH Control Sequencer initialize sa...

Page 126: ...xternal source between the minimum VDDA spec and the VDDA potential VREFH must never exceed VDDA 10 2 4 Voltage Reference Low VREFL VREFL is the low reference voltage for the converter In some package...

Page 127: ...CSC1 when software triggered operation is selected or one conversion following assertion of ADHWT when hardware triggered operation is selected 1 Continuous conversions initiated following a write to...

Page 128: ...lect Selects the type of trigger used for initiating a conversion Two types of triggers are selectable software trigger and hardware trigger When software trigger is selected a conversion is initiated...

Page 129: ...lost In 8 bit mode there is no interlocking with ADCRL If the MODE bits are changed any data in ADCRH becomes invalid 10 3 4 Data Result Low Register ADCRL ADCRL contains the lower eight bits of a 12...

Page 130: ...pare 10 3 6 Compare Value Low Register ADCCVL This register holds the lower eight bits of the 12 bit or 10 bit compare value or all eight bits of the 8 bit compare value When the compare function is e...

Page 131: ...selects between long and short sample time This adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs Longer sa...

Page 132: ...Field Description 7 ADPC7 ADC Pin Control 7 ADPC7 controls the pin associated with channel AD7 0 AD7 pin I O control enabled 1 AD7 pin I O control disabled 6 ADPC6 ADC Pin Control 6 ADPC6 controls the...

Page 133: ...controls the pin associated with channel AD15 0 AD15 pin I O control enabled 1 AD15 pin I O control disabled 6 ADPC14 ADC Pin Control 14 ADPC14 controls the pin associated with channel AD14 0 AD14 pi...

Page 134: ...23 controls the pin associated with channel AD23 0 AD23 pin I O control enabled 1 AD23 pin I O control disabled 6 ADPC22 ADC Pin Control 22 ADPC22 controls the pin associated with channel AD22 0 AD22...

Page 135: ...perates with any of the conversion modes and configurations 10 4 1 Clock Select and Divide Control One of four clock sources can be selected as the clock source for the ADC module This clock source is...

Page 136: ...dge occurs the rising edge is ignored In continuous convert configuration only the initial rising edge to launch continuous conversions is observed The hardware trigger function operates in conjunctio...

Page 137: ...rsion in progress is aborted when A write to ADCSC1 occurs the current conversion will be aborted and a new conversion will be initiated if ADCH are not all 1s A write to ADCSC2 ADCCFG ADCCVH or ADCCV...

Page 138: ...ersion time for a single conversion is NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications Table 10 13 Total Conversion Time vs Control Conditions Conver...

Page 139: ...peration Upon completion of a conversion while the compare function is enabled if the compare condition is not true COCO is not set and no data is transferred to the result registers NOTE The compare...

Page 140: ...e value of Result Compare Value 10 4 6 MCU Wait Mode Operation Wait mode is a lower power consumption standby mode from which recovery is fast because the clock sources remain active If a conversion i...

Page 141: ...cleared when entering stop3 and continuing ADC conversions 10 4 8 MCU Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters stop2 mode All module registers contain their r...

Page 142: ...4 ADLSMP 1 Configures for long sample time Bit 3 2 MODE 10 Sets mode at 10 bit conversions Bit 1 0 ADICLK 00 Selects bus clock as input clock source ADCSC2 0x00 00000000 Bit 7 ADACT 0 Flag indicates...

Page 143: ...associated with the ADC module and how they should be used for best results 10 6 1 1 Analog Supply Pins The ADC module has analog power and ground supplies VDDA and VSSA available as separate pins on...

Page 144: ...tor is connected between VREFH and VREFL and must be placed as near as possible to the package pins Resistance in the path is not recommended because the current causes a voltage drop that could resul...

Page 145: ...Leakage on the I O pins can cause conversion error if the external analog source resistance RAS is high If this error cannot be tolerated by the application keep RAS lower than VDDA 2N ILEAK for less...

Page 146: ...the result For 8 bit or 10 bit conversions the code transitions when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual t...

Page 147: ...ter is when at certain points a given input voltage converts to one of two values when sampled repeatedly Ideally when the input voltage is infinitesimally smaller than the transition voltage the conv...

Page 148: ...Analog to Digital Converter S08ADC12V1 MC9S08QL8 MCU Series Reference Manual Rev 1 148 NXP Semiconductors...

Page 149: ...is FLL clock or either of the internal or external reference clocks as a source for the MCU system clock There are also signals provided to control a low power oscillator XOSCVLP module to allow the u...

Page 150: ...ichever clock is selected as the source can be divided down 2 bit select for clock divider is provided Allowable dividers are 1 2 4 8 Control signals for a low power oscillator clock generator OSCOUT...

Page 151: ...aged external mode the ICS supplies a clock derived from the FLL which is controlled by an external reference clock source The BDC clock is supplied from the FLL 11 1 4 3 FLL Bypassed Internal FBI In...

Page 152: ...and the ICS supplies a clock derived from the external reference clock The BDC clock is not available 11 1 4 7 Stop STOP In stop mode the FLL is disabled and the internal or the ICS external reference...

Page 153: ...vide down the external reference clock Resulting frequency must be in the range 31 25 kHz to 39 0625 kHz See Table 11 3 for the divide by factors 2 IREFS Internal Reference Select The IREFS bit select...

Page 154: ...the external oscillator 4 HGO High Gain Oscillator Select The HGO bit controls the external oscillator mode of operation 1 Configure external oscillator for high gain operation 0 Configure external os...

Page 155: ...ng reset from a factory programmed location when not in any BDM mode If in a BDM mode FTRIM gets loaded with a value of 1 b0 W DRS Reset 0 0 0 1 0 0 0 Figure 11 5 ICS Status and Control Register ICSSC...

Page 156: ...If the external reference clock is selected by ERCLKEN or by the ICS being in FEE FBE or FBELP mode and if EREFS is set then this bit is set after the initialization cycles of the external oscillator...

Page 157: ...clock is derived from the FLL clock which is controlled by the internal reference clock The FLL loop locks the frequency to the FLL factor times the internal reference frequency The ICSLCLK is availab...

Page 158: ...LL bypassed internal mode the ICSOUT clock is derived from the internal reference clock The FLL clock is controlled by the internal reference clock and the FLL loop locks the FLL frequency to the FLL...

Page 159: ...signals are static except in the following cases ICSIRCLK will be active in stop mode when all the following conditions occur IRCLKEN bit is written to 1 IREFSTEN bit is written to 1 OSCOUT will be ac...

Page 160: ...used as an additional clock source To re target the ICSIRCLK frequency write a new value to the TRIM bits in the ICSTRM register to trim the period of the internal reference clock Writing a larger val...

Page 161: ...imum frequency the chip level timing specifications support see Chapter 1 Device Overview If EREFSTEN is set and the ERCLKEN bit is written to 1 the external reference clock source OSCOUT keeps runnin...

Page 162: ...Internal Clock Source S08ICSV3 MC9S08QL8 MCU Series Reference Manual Rev 0 162 NXP Semiconductors...

Page 163: ...based software loops 12 1 1 MTIM TPM Configuration Information The external clock for the MTIM module TCLK is selected by setting CLKS 1 1 or 1 0 in MTIMCLK which selects the TCLK pin input The TCLK...

Page 164: ...he MTIM can be used to bring the MCU out of wait mode if the timer overflow interrupt is enabled For lowest possible current consumption the MTIM should be stopped by software if not needed as an inte...

Page 165: ...hronized by the bus clock Also variations in duty cycle and clock jitter must be accommodated Therefore the TCLK signal must be limited to one fourth of the bus frequency The TCLK pin can be muxed wit...

Page 166: ...mary in the Memory chapter of this data sheet for the absolute address assignments for all MTIM registers This section refers to registers and control bits only by their names and relative address off...

Page 167: ...register 0 MTIM counter has not reached the overflow value in the MTIM modulo register 1 MTIM counter has reached the overflow value in the MTIM modulo register 6 TOIE MTIM Overflow Interrupt Enable...

Page 168: ...et clears CLKS to 000 00 Encoding 0 Bus clock BUSCLK 01 Encoding 1 Fixed frequency clock XCLK 10 Encoding 3 External source TCLK pin falling edge 11 Encoding 4 External source TCLK pin rising edge All...

Page 169: ...ld Description 7 0 COUNT MTIM Count These eight read only bits contain the current value of the 8 bit counter Writes have no effect to this register Reset clears the count to 0x00 7 6 5 4 3 2 1 0 R MO...

Page 170: ...cale values are software selectable clock source divided by 1 2 4 8 16 32 64 128 or 256 The prescaler select bits PS 3 0 in MTIMSC select the desired prescale value If the counter is active TSTP 0 whe...

Page 171: ...cted clock source could be any of the five possible choices The prescaler is set to PS 0010 or divide by 4 The modulo value in the MTIMMOD register is set to 0xAA When the counter MTIMCNT reaches the...

Page 172: ...Modulo Timer S08MTIMV1 MC9S08QL8 MCU Series Reference Manual Rev 1 172 NXP Semiconductors...

Page 173: ...odule on MC9S08QL8 series can be clocked from the ICSIRCLK OSCOUT or the LPO ICSIRCLK is connected to the IRCLK input and OSCOUT is connected to ERCLK input ICSERCLK is not available as a source to th...

Page 174: ...errupt is enabled For lowest possible current consumption the RTC should be stopped by software if not needed as an interrupt source during wait mode 13 1 7 2 Stop Modes The RTC continues to run in st...

Page 175: ...er Refer to the direct page register summary in the memory section of this document for the absolute address assignments for all RTC registers This section refers to registers and control bits only by...

Page 176: ...TC prescaler Changing the clock source clears the prescaler and RTCCNT counters When selecting a clock source ensure that the clock source is properly enabled if applicable to ensure correct operation...

Page 177: ...LPO the external clock ERCLK and the internal clock IRCLK The RTC clock select bits RTCLKS select the desired clock source If a different value is written to RTCLKS the prescaler and RTCCNT counters a...

Page 178: ...for an interrupt to be generated when RTIF is set To enable the real time interrupt set the real time interrupt enable bit RTIE in RTCSC RTIF is cleared by writing a 1 to RTIF 13 4 1 RTC Operation Ex...

Page 179: ...direction to a user on how to initialize and configure the RTC module The example software is implemented in C language The example below shows how to implement time of day with the RTC using the 1 kH...

Page 180: ...onductors pragma TRAP_PROC void RTC_ISR void Clear the interrupt flag RTCSC byte RTCSC byte 0x80 RTC interrupts every 1 Second Seconds 60 seconds in a minute if Seconds 59 Minutes Seconds 0 60 minutes...

Page 181: ...is not available in this device 14 1 1 SCI Clock Gating The bus clock to the SCI can be gated on and off using the SCI bit in SCGC1 This bit is set after any reset which enables the bus clock to this...

Page 182: ...E SCID Read Rx data write Tx data R5 T5 R7 T7 R6 T6 Rx Tx pin direction in Local interrupt enables R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 TXINV Tx data path polarity single wire mode Module Initialization Writ...

Page 183: ...error framing error and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and checking Programmable 8 bit or 9 bit character length Re...

Page 184: ...7 6 5 4 3 2 1 0 L SCID Tx BUFFER WRITE ONLY INTERNAL BUS STOP 11 BIT TRANSMIT SHIFT REGISTER START SHIFT DIRECTION LSB 1 BAUD RATE CLOCK PARITY GENERATION TRANSMIT CONTROL SHIFT ENABLE PREAMBLE ALL 1s...

Page 185: ...BUS STOP 11 BIT RECEIVE SHIFT REGISTER START SHIFT DIRECTION LSB FROM RxD PIN RATE CLOCK Rx INTERRUPT REQUEST DATA RECOVERY DIVIDE 16 BAUD SINGLE WIRE LOOP CONTROL WAKEUP LOGIC ALL 1s MSB FROM TRANSM...

Page 186: ...e so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled RE or TE bits in SCIC2 are written to 1 7 6 5 4 3 2 1 0 R LBKDIE RXEDGIE 0 SBR12 S...

Page 187: ...SCISWAI SCI Stops in Wait Mode 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU 1 SCI clocks freeze while CPU is in wait mode 5 RSRC Receive...

Page 188: ...TDRE flag is 1 6 TCIE Transmission Complete Interrupt Enable for TC 0 Hardware interrupts from TC disabled use polling 1 Hardware interrupt requested when TC flag is 1 5 RIE Receiver Interrupt Enable...

Page 189: ...ificant data bit in a character WAKE 1 address mark wakeup Application software sets RWU and normally a selected hardware condition automatically clears RWU Refer to Section 14 3 3 2 Receiver Wakeup O...

Page 190: ...r is all 1s these bit times and the stop bit time count toward the full character time of logic high 10 or 11 bit times depending on the M control bit needed for the receiver to detect an idle line Wh...

Page 191: ...circuitry is enabled and a LIN break character is detected LBKDIF is cleared by writing a 1 to it 0 No LIN break character has been detected 1 LIN break character has been detected 6 RXEDGIF RxD Pin A...

Page 192: ...waiting for a start bit 1 SCI receiver active RxD input not idle 1 Setting RXINV inverts the RxD input for all cases data bits start and stop bits break and idle 7 6 5 4 3 2 1 0 R R8 T8 TXDIR TXINV OR...

Page 193: ...rate clock 4 TXINV1 Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable...

Page 194: ...2 The transmitter output TxD idle state defaults to logic high TXINV 0 following reset The transmitter output is inverted by setting TXINV 1 The transmitter is enabled by setting the TE bit in SCIC2...

Page 195: ...en write 1 to the TE bit This action queues an idle character to be sent as soon as the shifter is available As long as the character in the shifter does not finish while TE 0 the SCI transmitter neve...

Page 196: ...case of the start bit the bit is assumed to be 0 if at least two of the samples at RT3 RT5 and RT7 are 0 even if one or all of the samples taken at RT8 RT9 and RT10 are 1s If any sample in any bit ti...

Page 197: ...tically when the receiver detects a logic 1 in the most significant bit of a received character eighth bit in M 0 mode and ninth bit in M 1 mode Address mark wakeup allows messages to contain idle cha...

Page 198: ...lready set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun OR flag gets set instead the data along with any associated NF FE or PF condi...

Page 199: ...ometimes used to check software independent of connections in the external system to help isolate system problems In this mode the transmitter output is internally connected to the receiver input and...

Page 200: ...Serial Communications Interface S08SCIV4 MC9S08QL8 MCU Series Reference Manual Rev 1 200 NXP Semiconductors...

Page 201: ...n be repositioned under software control using TPMCH0PS bits in SOPT2 as shown in Table 15 1 15 1 4 TPM Clock Gating The bus clock to the TPM can be gated on and off using the TPM bit in SCGC1 This bi...

Page 202: ...ars this read coherency mechanism Does not clear this read coherency mechanism Read of TPMxCnVH L registers2 In BDM mode any read of TPMxCnVH L registers Returns the value of the TPMxCnVH L register I...

Page 203: ...TPMxMODH L 1 6 Produces a near 100 duty cycle Produces 0 duty cycle TPMxCnVH L is changed from 0x0000 to a non zero value7 Waits for the start of a new PWM period to begin using the new duty cycle set...

Page 204: ...0xFFFF Also when configuring the TPM modules it is best to write to TPMxSC before TPMxCnV as a write to TPMxSC resets the coherency mechanism on the TPMxCnV registers 8 For more information refer to S...

Page 205: ...TPM all channels to switch to center aligned PWM mode When center aligned PWM mode is selected input capture output compare and edge aligned PWM functions are not available on any channels of this TPM...

Page 206: ...signal is called center aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero This type of PWM is required for types of motors used in s...

Page 207: ...S MS0B MS0A counter reset CLKSB CLKSA 1 2 4 8 16 32 64 or 128 bus clock external clock synchronizer 16 bit comparator 16 bit latch channel 1 ELS1B ELS1A CH1IE CH1F TPM counter Port logic Interrupt log...

Page 208: ...e mode therefore allowing its use as a timer ELSnB ELSnA 0 0 For proper TPM operation the external clock frequency must not exceed one fourth of the bus clock frequency 15 2 1 2 TPMxCHn TPM Channel n...

Page 209: ...ut signal When ELSnB is set and ELSnA is cleared the TPMxCHn pin is forced high at the start of each new period TPMxCNT 0x0000 and it is forced low when the channel value register matches the TPM coun...

Page 210: ...gister matches the TPM counter and it is cleared when the TPM counter is counting down and the channel value register matches the TPM counter Figure 15 4 High true pulse of a center aligned PWM Figure...

Page 211: ...6 TOIE Timer overflow interrupt enable This read write bit enables TPM overflow interrupts If TOIE is set an interrupt is generated when TOF equals one Reset clears TOIE 0 TOF interrupts inhibited use...

Page 212: ...ions The coherency mechanism is automatically restarted by an MCU reset or any write to the timer status control register TPMxSC Reset clears the TPM counter registers Writing any value to TPMxCNTH or...

Page 213: ...to 0x0000 that results in a free running timer counter modulo disabled Writes to any of the registers TPMxMODH and TPMxMODL actually writes to buffer registers and the registers are updated with the v...

Page 214: ...e TPM channel n value registers When channel n is an edge aligned center aligned PWM channel and the duty cycle is set to 0 or 100 CHnF is not set even when the value in the TPM counter registers matc...

Page 215: ...that is driven in response to an output compare match or select the polarity of the PWM output If ELSnB and ELSnA bits are cleared the channel pin is not controlled by TPM This configuration can be u...

Page 216: ...econd byte is written If CLKSB and CLKSA are not cleared and in output compare mode the registers are updated after the second byte is written and on the next change of the TPM counter end of the pres...

Page 217: ...Counter Clock Source The 2 bit field CLKSB CLKSA in the timer status and control register TPMxSC disables the TPM counter or selects one of three clock sources to TPM counter Table 15 6 After any MCU...

Page 218: ...unter operates in up down counting mode Otherwise the counter operates as a simple up counter As an up counter the timer counter counts from 0x0000 through its terminal count and continues with 0x0000...

Page 219: ...and according to the value of CLKSB CLKSA bits If CLKSB and CLKSA are cleared the registers are updated when the second byte is written If CLKSB and CLKSA are not cleared the registers are updated at...

Page 220: ...wn counting mode of the timer counter CPWMS 1 The channel match value in TPMxCnVH TPMxCnVL determines the pulse width duty cycle of the PWM signal while the period is determined by the value in TPMxMO...

Page 221: ...t all active channels within a TPM must be used in CPWM mode when CPWMS is set The timer channel registers are buffered to ensure coherent 16 bit updates and to avoid unexpected PWM pulse widths Write...

Page 222: ...scription of Interrupt Operation For each interrupt source in the TPM a flag bit is set upon recognition of the interrupt condition such as timer overflow channel input capture or output compare event...

Page 223: ...annel is configured as an input capture channel the ELSnB ELSnA bits select if channel pin is not controlled by TPM rising edges falling edges or any edge as the edge that triggers an input capture ev...

Page 224: ...Timer Pulse Width Modulator S08TPMV3 MC9S08QL8 MCU Series Reference Manual Rev 1 224 NXP Semiconductors...

Page 225: ...into the target MCU via the single wire background debug interface 16 1 1 Forcing Active Background The method for forcing active background mode depends on the specific HCS08 derivative For the MC9S0...

Page 226: ...ow the CPU registers to be read or written and allow the user to trace one user instruction at a time or GO to the user program from active background mode Non intrusive commands can be executed at an...

Page 227: ...ed BKGD is a pseudo open drain pin and there is an on chip pullup so no external pullup resistor is required Unlike typical open drain pins the external RC time constant on this pin which is influence...

Page 228: ...ives the beginning of the bit time Ten target BDC clock cycles later the target senses the bit level on the BKGD pin Typically the host actively drives the pseudo open drain BKGD pin during host to ta...

Page 229: ...time as perceived by the target MCU The host initiates the bit time but the target HCS08 finishes it Because the target wants the host to receive a logic 0 it drives the BKGD pin low for 13 BDC clock...

Page 230: ...ve background mode while non intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program Table 16 1 shows all HCS08 BDC comma...

Page 231: ...ad data in the target to host direction WD 8 bits of write data in the host to target direction RD16 16 bits of read data in the target to host direction WD16 16 bits of write data in the host to targ...

Page 232: ...E2 RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non intrusive C2 WBKP Write BDCBKPT breakpoint register GO Active BDM 08 d Go to execute the user application program starting at the address curre...

Page 233: ...munications Typically the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several...

Page 234: ...registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU so they do not have addresses and cannot be accessed by user programs Some of the b...

Page 235: ...e commands 6 BDMACT Background Mode Active Status This is a read only status bit 0 BDM not active user application program running 1 BDM active and waiting for serial commands 5 BKPTEN BDC Breakpoint...

Page 236: ...and into active background mode where all BDC commands work Whenever the host forces the target MCU into active background mode the host should issue a READ_STATUS command to check that BDMACT 1 befo...

Page 237: ...ugh serial background mode debug commands not from user programs Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 3 SBDFR Register Field Description Field Description 0 BDFR Background Debug F...

Page 238: ...Development Support MC9S08QL8 MCU Series Reference Manual Rev 1 238 NXP Semiconductors...

Page 239: ......

Page 240: ...ustomer s applications and products and NXP accepts no liability for any vulnerability that is discovered Customers should implement appropriate design and operating safeguards to minimize the risks a...

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