NXP Semiconductors MC9S08QL4, Reference Manual

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MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 25
Chapter 3
Modes of Operation
3.1 Introduction
The operating modes of the MC9S08QL8 series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.
3.2 Features
• Active background mode for code development
• Run mode — CPU clocks can be run at full speed and the internal supply is fully regulated.
• LPRUN mode — CPU and peripheral clocks are restricted to 125 kHz at maximum and the internal
voltage regulator is in standby
• Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
• LPWAIT mode — CPU shuts down to conserve power; peripheral clocks are restricted to 125 kHz
in maximum and the internal voltage regulator is in standby
• Stop modes — System clocks are stopped and voltage regulator is in standby
— Stop3 — All internal circuits are powered for fast recovery
— Stop2 — Partial power down of internal circuits, RAM content is retained, I/O states held
3.3 Run Mode
This is the normal operating mode for the MC9S08QL8 series. In this mode, the CPU executes code from
internal memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after
reset.
3.3.1 Low Power Run Mode (LPRun)
In the low power run mode, the on-chip voltage regulator is put into its standby state. This state uses the
minimum power consumption necessary for CPU functionality. Power consumption is most reduced by
disabling the clocks to all unused peripherals by clearing the corresponding bits in the SCGC1 and SCGC2
registers.
Before entering this mode, the following conditions must be met:
• FBELP is the selected clock mode for the ICS.
• The HGO bit in the ICSC2 register is clear.
• The bus frequency is less than 125 kHz.