NXP Semiconductors MC9S08QL4, Reference Manual

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Internal Clock Source (S08ICSV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 0
154 NXP Semiconductors
11.3.2 ICS Control Register 2 (ICSC2)
4 16 512
5 32 1024
6 64 Reserved
7 128 Reserved
1
Reset default
7 6 5 4 3 2 1 0
R
BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
W
Reset: 0 1 0 0 0 0 0 0
Figure 11-3. ICS Control Register 2 (ICSC2)
Table 11-4. ICS Control Register 2 Field Descriptions
Field Description
7:6
BDIV
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This
controls the bus frequency.
00
Encoding 0 — Divides selected clock by 1.
01 Encoding 1 — Divides selected clock by 2 (reset default).
10 Encoding 2 — Divides selected clock by 4.
11 Encoding 3 — Divides selected clock by 8.
5
RANGE
Frequency Range Select — Selects the frequency range for the external oscillator.
1 High frequency range selected for the external oscillator.
0 Low frequency range selected for the external oscillator.
4
HGO
High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation.
0 Configure external oscillator for low power operation.
3
LP
Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes.
1 FLL is disabled in bypass modes unless BDM is active.
0 FLL is not disabled in bypass mode.
2
EREFS
External Reference Select — The EREFS bit selects the source for the external reference clock.
1 Oscillator requested.
0 External Clock Source requested.
1
ERCLKEN
External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK.
1 ICSERCLK active.
0 ICSERCLK inactive.
0
EREFSTEN
External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock
source (OSCOUT) remains enabled when the ICS enters stop mode.
1 External reference clock source stays enabled in stop if ERCLKEN is set before entering stop.
0 External reference clock source is disabled in stop.
Table 11-3. Reference Divide Factor
RDIV RANGE=0 RANGE=1