NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 5 Resets, Interrupts, and General System Control
MC9S08QL8 MCU Series Reference Manual, Rev. 1
72 NXP Semiconductors
5.8.8 System Power Management Status and Control 2 Register
(SPMSC2)
This high-page register contains status and control bits to configure the low power run and wait modes as
well as configure the stop mode behavior of the MCU. See
Section 3.3.1, Low Power Run Mode (LPRun) ,
Section 3.5.1, Low Power Wait Mode (LPWait) , and Section 3.6, Stop Modes for more information.
7 6 5 4 3 2 1 0
R
LPR
LPRS
LPWUI
0 PPDF 0
PPDE
1
PPDC
W PPDACK
Reset: 0 0 0 0 0 0 1 0
Stop2
wakeup:
0 0 u 0 1 0 1 1
= Unimplemented or Reserved u= Unaffected by reset
1. This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
Table 5-11. SPMSC2 Register Field Descriptions
Field Description
7
LPR
Low Power Regulator Control — The LPR bit controls entry into the low power run and wait modes in which
the voltage regulator is put into standby. This bit cannot be set if PPDC=1. If PPDC and LPR are set in a single
write instruction, only PPDC will actually be set. Automatically cleared when LPWUI is set and an interrupt
occurs.
0 Low power run and wait modes are disabled.
1 Low power run and wait modes are enabled.
6
LPRS
Low Power Regulator Status — This read-only status bit indicates that the voltage regulator has entered into
standby for the low power run or wait mode.
0 The voltage regulator is not currently in standby.
1 The voltage regulator is currently in standby.
5
LPWUI
Low Power Wake Up on Interrupt — This bit controls whether or not the voltage regulator exits standby when
any active MCU interrupt occurs.
0 The voltage regulator will remain in standby on an interrupt.
1 The voltage regulator will exit standby on an interrupt.
3
PPDF
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
2
PPDACK
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
1
PPDE
Partial Power Down Enable — The write-once PPDE bit can be used to “lockout” the partial power down mode.
0 Partial power down is not enabled.
1 Partial power down is enabled and controlled via the PPDC bit.
0
PPDC
Partial Power Down Control — The PPDC bit controls which power down mode is selected. This bit cannot be
set if LPR=1. If PPDC and LPR are set in a single write instruction, only PPDC will actually be set.
0 Stop3 low power mode enabled.
1 Stop2 partial power down mode enabled.