NXP Semiconductors MC9S08QL4, Reference Manual

Page: 221 / 240

Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 221
The channel match value in the TPM channel registers (times two) determines the pulse width (duty cycle)
of the CPWM signal (
Figure 15-15 ). If ELSnA is cleared, a channel match occurring while counting up
clears the CPWM output signal and a channel match occurring while counting down sets the output. The
counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down
until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
Figure 15-15. CPWM period and pulse width (ELSnA=0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.
Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is
operating in up/down counting mode so this implies that all active channels within a TPM must be used in
CPWM mode when CPWMS is set.
The timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM
pulse widths. Writes to any of the registers TPMxCnVH and TPMxCnVL actually write to buffer registers.
In center-aligned PWM mode, the TPMxCnVH:TPMxCnVL registers are updated with the value of their
write buffer according to the value of CLKSB:CLKSA bits:
• If CLKSB and CLKSA are cleared, the registers are updated when the second byte is written
• If CLKSB and CLKSA are not cleared, the registers are updated after both bytes were written, and
the TPM counter changes from (TPMxMODH:TPMxMODL – 1) to
(TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made
when the TPM counter changes from 0xFFFE to 0xFFFF.
When TPMxCNTH:TPMxCNTL equals TPMxMODH:TPMxMODL, the TPM can optionally generate a
TOF interrupt (at the end of this count).
15.5 Reset Overview
15.5.1 General
The TPM is reset whenever any MCU reset occurs.
period
pulse width
TPM counter =
TPM counter = 0
TPM counter = channel match
(count down)
channel match
(count up)
TPMxCHn
2

TPMxMODH:TPMxMODL
2

TPMxCnVH:TPMxCnVL
TPMxMODH:TPMxMODL
TPMxMODH:TPMxMODL