NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 15 Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
204 NXP Semiconductors
15.1.6 Migrating from TPMV1
In addition to Section 15.1.5, TPMV3 Differences from Previous Versions , keep in mind the following
considerations when migrating from a device that uses TPMV1.
• You can write to the Channel Value register (TPMxCnV) when the timer is not in input capture
mode for TPMV2, not TPMV3.
• In edge- or center- aligned modes, the Channel Value register (TPMxCnV) registers only update
when the timer changes from TPMMOD-1 to TPMMOD, or in the case of a free running timer
from 0xFFFE to 0xFFFF.
• Also, when configuring the TPM modules, it is best to write to TPMxSC before TPMxCnV as a
write to TPMxSC resets the coherency mechanism on the TPMxCnV registers.
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For more information, refer to Section 15.4.2.4, Center-Aligned PWM Mode . [SE110-TPM case 4]
Table 15-3. Migrating to TPMV3 Considerations
When... Action / Best Practice
Writing to the Channel Value Register (TPMxCnV)
register... Timer must be in Input Capture mode.
Updating the Channel Value Register (TPMxCnV)
register in edge-aligned or center-aligned modes... Only occurs when the timer changes from
TPMMOD-1 to TPMMOD (or in the case of a free
running timer, from 0xFFFE to 0xFFFF).
Reseting the coherency mechanism for the
Channel Value Register (TPMxCnV) register... Write to TPMxSC.
Configuring the TPM modules... Write first to TPMxSC and then to TPMxCnV
register.