Chapter 3 Modes of Operation
MC9S08QL8 MCU Series Reference Manual, Rev. 1
26
NXP Semiconductors
•
If enabled, the ADC must be configured to use the asynchronous clock source, ADACK, to meet
the ADC minimum frequency requirements. The bandgap channel cannot be converted in low
power run mode.
•
The LVD and LVW must be disabled by clearing either the LVDE or LVDSE bits in the SPMSC1
register.
•
Flash programming/erasing is not allowed.
•
ACMP option to compare to internal bandgap reference is not allowed in LPRUN and LPWAIT.
Once these conditions are met, low power run mode can be entered by setting the LPR bit in the SPMSC2
register.
To re-enter standard run mode, clear the LPR bit. The LPRS bit in the SPMSC2 register is a read-only
status bit that can be used to determine if the regulator is in full regulation mode or not. When LPRS is ‘0’,
the regulator is in full regulation mode and the MCU can run at full speed in any clock mode.
3.3.1.1
Interrupts in Low Power Run Mode
Low power run mode provides the option to return to full regulation if any interrupt occurs. This is done
by setting the LPWUI bit in the SPMSC2 register. The ICS can then be set for full speed immediately in
the interrupt service routine.
If the LPWUI bit is clear, interrupts will be serviced in low power run mode.
If the LPWUI bit is set, LPR and LPRS bits will be cleared and interrupts will be serviced with the
regulator in full regulation.
3.3.1.2
Resets in Low Power Run Mode
Any reset will exit low power run mode, clear the LPR and LPRS bits, and return the device to normal run
mode.
3.4
Active Background Mode
The active background mode functions are managed through the BDC in the HCS08 core. The BDC
provides the means for analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
•
When the BKGD/MS pin is low during POR
•
When the BKGD/MS pin is low immediately after issuing a background debug force reset (see
Section 5.8.3, System Background Debug Force Reset Register (SBDFR)
).
•
When a BACKGROUND command is received through the BKGD/MS pin
•
When a BGND instruction is executed
•
When encountering a BDC breakpoint
After entering active background mode, the CPU is held in a suspended state while it waits for serial
background commands instead of executing instructions from the user application program.
Background commands are of two types:
Summary of Contents for MC9S08QL4
Page 4: ...MC9S08QL8 MCU Series Reference Manual Rev 1 4 NXP Semiconductors...
Page 36: ...Chapter 3 Modes of Operation MC9S08QL8 MCU Series Reference Manual Rev 1 36 NXP Semiconductors...
Page 56: ...Chapter 4 Memory MC9S08QL8 MCU Series Reference Manual Rev 1 56 NXP Semiconductors...
Page 172: ...Modulo Timer S08MTIMV1 MC9S08QL8 MCU Series Reference Manual Rev 1 172 NXP Semiconductors...
Page 238: ...Development Support MC9S08QL8 MCU Series Reference Manual Rev 1 238 NXP Semiconductors...
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