NXP Semiconductors MC9S08QL4, Reference Manual

Page: 86 / 240

Chapter 6 Parallel Input/Output Control
MC9S08QL8 MCU Series Reference Manual, Rev. 1
86 NXP Semiconductors
6.4.3.2 Port C Data Direction Register (PTCDD)
Table 6-11. PTCD Register Field Descriptions
Field Description
3:0
PTCD[3:0]
Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out of the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out of the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7 6 5 4 3 2 1 0
R
— — — — PTCDD3 PTCDD2 PTCDD1 PTCDD0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-13. Port C Data Direction Register (PTCDD)
Table 6-12. PTCDD Register Field Descriptions
Field Description
3:0
PTCDD[3:0]
Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.