NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 5 Resets, Interrupts, and General System Control
MC9S08QL8 MCU Series Reference Manual, Rev. 1
68 NXP Semiconductors
5.8.4 System Options Register 1 (SOPT1)
This high-page register is a write-once register, so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. SOPT1 must be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
7 6 5 4 3 2 1 0
R
COPE COPT STOPE
0 0 0
BKGDPE RSTPE
W
Reset: 1 1 0 0 0 0 1 u
1
POR: 1 1 0 0 0 0 1 0
LVR: 1 1 0 0 0 0 1 0
= Unimplemented or Reserved
1. u = unaffected
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-6. SOPT1 Register Field Descriptions
Field Description
7
COPE
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE
Background Debug Mode Pin Enable — This write-once bit when set enables the PTA4/ACMPO/BKGD/MS
pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This
pin defaults to the BKGD/MS function following any MCU reset.
0 PTA4/ACMPO/BKGD/MS pin functions as PTA4 or ACMPO
1 PTA4/ACMPO/BKGD/MS pin functions as BKGD/MS.
0
RSTPE
1
1
The RSTPE bit will be cleared by the stop2 recovery and must not be set before writing to the PPDACK bit. Doing so will cause
a second reset event and the PPDF bit will be cleared at the end of the second reset. The RESET pin must be monitored by
reading PTA5 port as input so that RSTPE is enabled only after the pin is confirmed as "1". By doing so, RESET pin can avoid
being low and cause another reset. Mind that COP must be refreshed during pin monitor to prevent unwanted COP reset.
RESET Pin Enable — This write-once bit when set enables the PTA5/IRQ/TCLK/RESET pin to function as
RESET. When clear, the pin functions as one of its input only alternative functions. This pin defaults to its PTA5
function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTA5/IRQ/TCLK/RESET pin functions as PTA5, IRQ or TCLK.
1 PTA5/IRQ/TCLK/RESET pin functions as RESET.