NXP Semiconductors MC9S08QL4, Reference Manual

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Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
218 NXP Semiconductors
15.4.1.2 Counter Overflow and Modulo Reset
An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a
software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE = 0) where no interrupt is generated, or interrupt-driven operation (TOIE = 1)
where the interrupt is generated whenever the TOF is set.
The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned
PWM (CPWMS = 1). If CPWMS is cleared and there is no modulus limit, the 16-bit timer counter counts
from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF is set at the
transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF is set at the transition from the value
set in the modulus register to 0x0000. When the TPM is in center-aligned PWM mode (CPWMS = 1), the
TOF flag is set as the counter changes direction at the end of the count value set in the modulus register
(at the transition from the value set in the modulus register to the next lower count value). This corresponds
to the end of a PWM period (the 0x0000 count value corresponds to the center of a period).
15.4.1.3 Counting Modes
The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1),
the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter.
As an up counter, the timer counter counts from 0x0000 through its terminal count and continues with
0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.
When center-aligned PWM operation is specified, the counter counts up from 0x0000 through its terminal
count and then down to 0x0000 where it changes back to up counting. The terminal count value and
0x0000 are normal length counts (one timer clock period long). In this mode, the timer overflow flag
(TOF) is set at the end of the terminal-count period (as the count changes to the next lower count value).
15.4.1.4 Manual Counter Reset
The main timer counter can be manually reset at any time by writing any value to TPMxCNTH or
TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only half
of the counter was read before resetting the count.
15.4.2 Channel Mode Selection
If CPWMS is cleared, MSnB and MSnA bits determine the basic mode of operation for the corresponding
channel. Choices include input capture, output compare, and edge-aligned PWM.
15.4.2.1 Input Capture Mode
With the input capture function, the TPM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter
into the channel-value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge is
chosen as the active edge that triggers an input capture.
In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only.