NXP Semiconductors MC9S08QL4, Reference Manual

Page: 9 / 240

MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 9
10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................126
10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................128
10.3.3 Data Result High Register (ADCRH) .............................................................................129
10.3.4 Data Result Low Register (ADCRL) ..............................................................................129
10.3.5 Compare Value High Register (ADCCVH) ....................................................................130
10.3.6 Compare Value Low Register (ADCCVL) .....................................................................130
10.3.7 Configuration Register (ADCCFG) ................................................................................130
10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................132
10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................133
10.3.10Pin Control 3 Register (APCTL3) ..................................................................................134
10.4 Functional Description ..................................................................................................................135
10.4.1 Clock Select and Divide Control ....................................................................................135
10.4.2 Input Select and Pin Control ...........................................................................................136
10.4.3 Hardware Trigger ............................................................................................................136
10.4.4 Conversion Control .........................................................................................................136
10.4.5 Automatic Compare Function .........................................................................................139
10.4.6 MCU Wait Mode Operation ............................................................................................140
10.4.7 MCU Stop3 Mode Operation ..........................................................................................140
10.4.8 MCU Stop2 Mode Operation ..........................................................................................141
10.5 Initialization Information ..............................................................................................................141
10.5.1 ADC Module Initialization Example .............................................................................141
10.6 Application Information ................................................................................................................143
10.6.1 External Pins and Routing ..............................................................................................143
10.6.2 Sources of Error ..............................................................................................................145
Chapter 11
Internal Clock Source (S08ICSV3)
11.1 Introduction ...................................................................................................................................149
11.1.1 DCO Select bits ..............................................................................................................149
11.1.2 Features ...........................................................................................................................150
11.1.3 Block Diagram ................................................................................................................150
11.1.4 Modes of Operation ........................................................................................................151
11.2 External Signal Description ..........................................................................................................152
11.3 Register Definition ........................................................................................................................152
11.3.1 ICS Control Register 1 (ICSC1) .....................................................................................153
11.3.2 ICS Control Register 2 (ICSC2) .....................................................................................154
11.3.3 ICS Trim Register (ICSTRM) .........................................................................................155
11.3.4 ICS Status and Control (ICSSC) .....................................................................................155
11.4 Functional Description ..................................................................................................................157
11.4.1 Operational Modes ..........................................................................................................157
11.4.2 Mode Switching ..............................................................................................................159
11.4.3 Bus Frequency Divider ...................................................................................................160
11.4.4 Low Power Bit Usage .....................................................................................................160
11.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................160
11.4.6 Internal Reference Clock ................................................................................................160