NXP Semiconductors MC9S08QL4, Reference Manual

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Analog-to-Digital Converter (S08ADC12V1)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
130 NXP Semiconductors
10.3.5 Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. When the
compare function is enabled, these bits are compared to the upper four bits of the result following a
conversion in 12-bit mode.
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]).
These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the
compare function is enabled.
In 8-bit mode, ADCCVH is not used during compare.
10.3.6 Compare Value Low Register (ADCCVL)
This register holds the lower eight bits of the 12-bit or 10-bit compare value or all eight bits of the 8-bit
compare value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower eight
bits of the result following a conversion in 12-bit, 10-bit or 8-bit mode.
10.3.7 Configuration Register (ADCCFG)
ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and
long sample time.
7 6 5 4 3 2 1 0
R 0 0 0 0
ADCV11 ADCV10 ADCV9 ADCV8
W
Reset: 0 0 0 0 0 0 0 0
Figure 10-6. Compare Value High Register (ADCCVH)
7 6 5 4 3 2 1 0
R
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
W
Reset: 0 0 0 0 0 0 0 0
Figure 10-7. Compare Value Low Register(ADCCVL)
7 6 5 4 3 2 1 0
R
ADLPC ADIV ADLSMP MODE ADICLK
W
Reset: 0 0 0 0 0 0 0 0
Figure 10-8. Configuration Register (ADCCFG)