NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 3 Modes of Operation
MC9S08QL8 MCU Series Reference Manual, Rev. 1
28 NXP Semiconductors
3.5.1.1 Interrupts in Low Power Wait Mode
If the LPWUI bit is set when the WAIT instruction is executed, then the voltage regulator will return to
full regulation when wait mode is exited. The ICS can be set for full speed immediately in the interrupt
service routine.
If the LPWUI bit is clear when the WAIT instruction is executed, an interrupt will return the device to low
power run mode.
If the LPWUI bit is set when the WAIT instruction is executed, an interrupt will return the device to normal
run mode with full regulation and the LPR and LPRS bits will be cleared.
3.5.1.2 Resets in Low Power Wait Mode
Any reset will exit low power wait mode, clear the LPR and LPRS bits, and return the device to normal
run mode.
3.6 Stop Modes
One of two stop modes (stop2 or stop3) is entered upon execution of a STOP instruction when the STOPE
bit in the system option 1 register (SOPT1) is set. In both stop modes, the bus and CPU clocks are halted.
In stop3 the voltage regulator is in standby. In stop2 the voltage regulator is in partial powerdown. The ICS
module can be configured to leave the reference clocks running. See
Chapter 11, Internal Clock Source
(S08ICSV3) for more information.
If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter either stop
mode and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in
the System Power Management Status and Control 2 Register (SPMSC2).
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection
Register SOPT1 BDCSCR SPMSC1 SPMSC2
Stop Mode
Bit name STOPE ENBDM
1
1
ENBDM is located in the BDCSCR which is accessible only through BDC commands, see Chapter 16, Development
Support .
LVDE LVDSE PPDC
0 x x x Stop modes disabled; illegal opcode reset if STOP
instruction executed
1 1 x x Stop3 with BDM enabled
2
2
When in stop3 mode with BDM enabled, The S
IDD
will be near R
IDD
levels because internal clocks are enabled.
1 0 Both bits must be 1 x Stop3 with voltage regulator active
1 0 Either bit a 0 0 Stop3
1 0 Either bit a 0 1 Stop2