NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 3 Modes of Operation
MC9S08QL8 MCU Series Reference Manual, Rev. 1
30 NXP Semiconductors
The voltage regulator recovery time (t
VRR
) is provided in the data sheet. This time is not influenced by the
clock source frequency or V
DD
and is therefore relatively consistent.
Since exiting from stop2 causes the MCU to wake as if a POR occurred, the standard reset processing will
always occur which takes about 150 ICSOUT cycles after the clock source has started. Therefore, the
equation for stop2 recovery time is
Stop2 recovery time = t
VRR
+ clock start up time + 150 ICSOUT cycles. Eqn. 3-1
Since ICSOUT defaults to FLL output running at 8.4 MHz during a reset, and the FLL takes about 1 ms
to start outputting a clock signal (although it won’t be stable initially)
Equation 3-5 simplifies to
Stop2 recovery time = t
VRR
+ 1

sec + 17.9

s. Eqn. 3-2
3.6.2 Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions shown in Table 3-1 . The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the RTC,
LVD, LVW, ADC, ACMP, IRQ, SCI or the KBI.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.2.1 Stop3 Mode Recovery Time
The stop3 recovery time is defined as the interval from the exit trigger to the first opcode fetch. There are
three main components to this wakeup time: the voltage regulator recovery time, the clock source start up
time, and the reset or interrupt processing time.
The voltage regulator recovery time (t
VRR
) is provided in the data sheet. This time is not influenced by the
clock source frequency or V
DD
and is therefore relatively consistent.
When an interrupt is used as the exit trigger, the clock must restart and ICSOUT must oscillate six times
before the interrupt processing begins. The interrupt processing requires 11 bus cycles (22 ICSOUT
cycles) for the stacking and vector fetch. Therefore, the first opcode of the interrupt service routine (ISR)
will begin after
Stop3 recovery time = t
VRR
+ clock start up time + 28 ICSOUT cycles. Eqn. 3-3
The clock source start up time is dependent on the clock mode selected when the MCU enters stop mode.
When the FLL output is selected as the clock source, the FLL starts up within a microsecond at roughly
the same frequency as before stop mode is entered. Typical start up time for the internal reference is given
in the data sheet. Typical start up times for the crystal oscillator are also given in the data sheet.
Assuming the FLL is the selected clock source upon entering stop3 and the FLL is configured for a
20 MHz ICSOUT frequency, then
Equation 3-6 simplifies to