NXP Semiconductors MC9S08QL4, Reference Manual

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Chapter 7 Keyboard Interrupt (S08KBIV2)
MC9S08QL8 MCU Series Reference Manual, Rev. 1
92 NXP Semiconductors
7.3 Register Definition
The KBI includes three registers:
• An 8-bit pin status and control register.
• An 8-bit pin enable register.
• An 8-bit edge select register.
Refer to the direct-page register summary in Chapter 4, Memory for the absolute address assignments for
all KBI registers. This section refers to registers and control bits only by their names and relative address
offsets.
7.3.1 KBI Interrupt Status and Control Register (KBISC)
7 6 5 4 3 2 1 0
R 0 0 0 0 KBF 0
KBIE KBIMOD
W KBACK
Reset: 0 0 0 0 0 0 0 0
Figure 7-2. KBI Interrupt Status and Control Register (KBISC)
Table 7-2. KBISC Register Field Descriptions
Field Description
3
KBF
KBI Interrupt Flag — KBF indicates when a KBI interrupt is detected. Writes have no effect on KBF.
0 No KBI interrupt detected.
1 KBI interrupt detected.
2
KBACK
KBI Interrupt Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always
reads as 0.
1
KBIE
KBI Interrupt Enable — KBIE determines whether a KBI interrupt is requested.
0 KBI interrupt request not enabled.
1 KBI interrupt request enabled.
0
KBIMOD
KBI Detection Mode — KBIMOD (along with the KBIES bits) controls the detection mode of the KBI interrupt
pins.
0 KBI pins detect edges only.
1 KBI pins detect both edges and levels.