NEC V850E/PH2, User Manual

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Chapter 17 Clocked Serial Interface 3 (CSI3)
User’s Manual U16580EE3V1UD00
17.6.2 Single mode (master mode, reception mode)
Figure 17-23: Single Mode (Master Mode, Reception Mode)
MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 1
Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B)
INTC3n Interrupt Not Delayed (CSIT bit = 0),
Transfer Wait: Disabled (CSWE bit = 0),
Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
Notes: 1. While the SIRB3n register is full a new transfer start of reception from the slave is put on
hold until the SIRB3n register is read.
2. During this period a reception from the slave is put on hold until at least one dummy
transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register
(SFEMPn flag of SFA3n register = 0) in order to start the transfer.
Remark:
μ
PD70F3187: n = 0, 1
μ
PD70F3447: n = 0
CRXEn bit
SFDB3n
register write
CSIBUF3n [0]
dummy
55H
CS0 CS1 CS2
AAH
CSIBUF3n [1]
CSIBUF3n [2]
SCK3n pin
SI3n pin
CSOTn flag
INTC3n signal
SIRB3n
register
SIRB3n
register read
SCS3n0 to
SCS3n3 pins
H (inactive)
CCH
<1>
<2>
<3>
<4> <5> <6> <6> <7> <7> <7>
Note 2 Note 1
<6>
<8>
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0
dummy
dummy
0H 0H 0H 1H 1H 1H 2H
SFEMPn flag
SFP3 to
SFP0 bits
0