NEC V850E/PH2, User Manual

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Chapter 3 CPU Functions
User’s Manual U16580EE3V1UD00
(2) NMI status saving registers (FEPC, FEPSW)
There are two NMI status saving registers, FEPC and FEPSW.
Upon occurrence of a non-maskable interrupt (NMI), the content of the program counter (PC) is
saved to FEPC and the content of the program status word (PSW) is saved to FEPSW.
The address of the next instruction following the instruction executed when a non-maskable
interrupt occurs is saved to FEPC, except for the DIVH instruction.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function
expansion.
Figure 3-4: NMI Status Saving Registers (FEPC, FEPSW)
The values of FEPC and FEPSW are restored to PC and PSW during execution of a RETI
instruction.
(3) Exception cause register (ECR)
Upon occurrence of an interrupt or an exception, the Exception Cause Register (ECR) holds the
source of the interrupt or the exception. The value held by ECR is an exception code, coded for
each interrupt source. This register is a read-only register, and thus data cannot be written to it
using the LDSR instruction.
Figure 3-5: Interrupt Source Register (ECR)
The list of exception codes is tabulated in Table 7-1, “Interrupt/Exception Source List,” on
page 219 .
31 26 25 0
After reset
0xxxxxxxH
(x: Undefined)
FEPC 0 0 0 0 0 0 (PC contents)
31 8 7 0
After reset
000000xxH
(x: Undefined)
FEPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents)
31 16 15 0
After reset
00000000H
ECR FECC EICC
Bit position Bit name Description
31 to 16 FECC Non-maskable interrupt (NMI) exception code
15 to 0 EICC Exception, maskable interrupt exception code