NEC V850E/PH2, User Manual

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Chapter 11 16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
(8) TMTn option register 0 (TTnOPT0)
The TTnOPT0 register is an 8-bit register that sets the capture/compare operation and detects
overflow.
This register can be read and written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Set the bits of the TTnOPT0 register other than TTnOVF when TTnCE = 0. When TTnCE = 1,
write access of bits of the TTnOPT0 register other than TTnOVF can be performed using the same
value.
Figure 11-13: TMTn Option Register 0 (TTnOPT0)
Remark: n = 0, 1
After reset: 00H R/W Address: TT0OPT0 FFFFF697H,
TT1OPT1 FFFFF6A7H
7 6 5 4 3 2 1 0
TTnOPT0 0 0 TTnCCS1 TTnCCS0 0 0 0 TTnOVF
(n = 0, 1)
TTnCCS1 Specifies the operation mode of register TTnCCR1
0 Operation as compare register
1 Operation as capture register
Remark: The setting of bit TTnCCS1 is valid in the free-running mode only.
TTnCCS0 Specifies the operation mode of register TTnCCR0
0 Operation as compare register
1 Operation as capture register
Remark: The setting of bit TTnCCS0 is valid in the free-running mode only.
TTnOVF Flag that indicates TMTn overflow
0 No overflow occurrence after timer restart or flag reset
1 Overflow occurrence
In the free-running mode, pulse width measurement mode, and offset trigger generation
mode, if the counter value is counted up from FFFFH, overflow occurs, the TTnOVF flag is
set (1), and the counter is cleared to 0000H. The counter is also cleared by writing 0. At
the same time that the TTnOVF flag is set (1), an overflow interrupt (INTTTnOV) occurs.
If 0 is written to the TTnOVF flag, or if TTnECC = 0 and TTnCE = 0 are set, the counter is
cleared.
Remark: Overflow does not occur during compare match & clear operation for counter
value FFFFH and compare value FFFFH.
Cautions: 1. If overflow occurs in the encoder compare mode, the encoder-dedi-
cated overflow flag (TTnEOF) is set, and the overflow flag (TTnOVF) is
not set. At this time, the overflow interrupt (INTTTnOV) is output.
2. When TTnOVF = 1, the TTnOVF flag is not cleared even if the TTnOVF
flag and TTnOPT0 register are read.
3. The TTnOVF flag can be read and written, but even if 1 is written to
the TTnOVF flag from the CPU, this is invalid.