NEC V850E/PH2, User Manual

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Chapter 3 CPU Functions
User’s Manual U16580EE3V1UD00
3.3 Operating Modes
The V850E/PH2 has the following operating modes.
3.3.1 Operating modes outline
(1) Normal operating mode
(a) Single-chip mode 0
Access to the internal ROM is enabled.
In single-chip mode 0, after the system reset is released, each pin related to the bus interface
enters the port mode, program execution branches to the reset entry address of the internal ROM,
and instruction processing starts. By setting the PMCDH, PMCDL, PMCCS, PMCCT, and PMCCM
registers to control mode by instruction, an external device can be connected to the external mem-
ory area.
(b) Single-chip mode 1 (
μ
PD70F3187 only)
In single-chip mode 1
Note
, after the system reset is released, each pin related to the bus interface
enters the control mode, program execution branches to the external device’s (memory) reset
entry address, and instruction processing starts. The internal ROM area is mapped from address
100000H.
(c) ROM-less mode (
μ
PD70F3187 only)
After the system reset is released, each pin related to the bus interface enters the control mode,
program execution branches to the external device’s (memory) reset entry address, and
instruction processing starts. Fetching of instructions and data access for internal ROM becomes
impossible.
In ROM-less mode the data bus width is 32 bits.
(2) Flash memory programming mode
In this mode the internal flash memory can be written or erased with an external flash writer, using
the CSIB0 or UARTC0 as serial interface.
Note: Single-chip mode 1 is not available on
μ
PD70F3447.