NEC V850E/PH2, User Manual

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Chapter 18 AFCAN Controller
User’s Manual U16580EE3V1UD00
Cautions: 1. Set IE bit and RDY bit always separately.
2. Do not set the DN bit to 1 by software. Be sure to write 0 to bit 10.
3. Do not set the TRQ bit and the RDY bit (1) at the same time. Set the RDY bit (1)
before setting the TRQ bit.
4. Do not clear the RDY bit (0) during message transmission. Follow the transmis-
sion abort process about clearing the RDY bit (0) for redefinition of the message
buffer.
5. Clear again when RDY bit is not cleared even if this bit is cleared.
6. Be sure that RDY is cleared before writing to the other message buffer registers,
by checking the status of the RDY bit.
Set TRQ Clear TRQ Setting of TRQ bit
0 1 TRQ bit is cleared to 0.
1 0 TRQ bit is set to 1.
Other than above TRQ bit is not changed.
Set RDY Clear RDY Setting of RDY bit
0 1 RDY bit is cleared to 0.
1 0 RDY bit is set to 1.
Other than above RDY bit is not changed.