NEC V850E/PH2, User Manual

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Chapter 11 16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
(4) Control through TTnCTL2 register
The settings of the TTnCTL2 register in the encoder compare mode
(TTnMD3 to TTnMD0 = 1000B) are as follows.
• In the case of bits TTnUDS1 and TTnUDS0, up/down judgment control is performed for the
phase input from pins TENCTn0 and TENCTn1.
• In the case of bits TTnECM1 and TTnECM0, counter clear control is performed upon a match
between the counter value and the compare setting value.
Bits TTnECM1 and TTnECM0 are valid in modes where the TTnCCR0 or TTnCCR1 register is
used as a compare-only register.
These bits are invalid in modes where the TTnCCR0 or TTnCCR1 register is used as a
capture-only register.
• The TTnLDE bit controls the function to load to the counter the setting value of the TTnCCR0
register upon occurrence of counter underflow.
Bit TTnLDE is valid only when the TTnECm bit setting is 00B, 01B, in a mode where the TTnCCR0
or TTnCCR1 register is used as a compare-only register.
In the case of all other settings, bit TTnLDE is invalid even if manipulated.
As an example of the use of the encoder count function, counter operation becomes possible
between the setting values of registers 0000H to TTnCCR0 by using the counter load functions
(TTnLDE = 1) indicated with “
•
” in the table, and the function for clearing the counter to 0000H in
case the count operation following a match with the TTnCCR0 buffer register is up count
(TTnECM0 = 1). (Refer to
11.6.9 (4) (c) Counter load function for TTnCCR0 register setting
value upon underflow (bit TTnLDE of register TTnCTL2)) ).
TTnMD3 to 0 TTnUDS1 to 0 TTnECM1 TTnECM0 TTnLDE Clear Load
1000B All settings
possible
00B
01B
10B
11B
0 0 0 - -
1
√
1 0 TTnCCR0 -
1
•
1 0 Invalid TTnCCR1 -
1 Invalid TTnCCR0
TTnCCR1 -