NEC V850E/PH2, User Manual

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Chapter 6 DMA Functions (DMA Controller)
User’s Manual U16580EE3V1UD00
Figure 6-15: Operation of DMA Channel 4/5
Note: DMA transfer completion interrupt has the same interrupt vector address as the corresponding
reception completion interrupt specified by DTFRX register, and replaces that interrupt.
Remark: n = 0, 1 (number of serial interface channel)
x = 4, 5 (number of DMA transfer channel)
Operation of DMA channel 4/5
DEx bit = 1 ?
DEx bit newly
written ?
DMA trigger
factor occurred ?
Transfer content from serial receive buffer
(depending on DTFRx register) to iRAM :
(MARx) SIRBn or CBnRX
Increment source pointer:
MARx MARx + 2
Decrement DMA transfer count register:
DTCRx DTCRx - 1
DTCRx = 0?
Set DMA transfer status bit: DMASx = 1
Generate interrupt signal (INTDMAx
Note
)
yes
no
yes
yes
no
no
yes
no
DMA transfer will be enabled by write
access to the corresponding DEn bit.
DMA trigger factor is the interrupt
source specified by DTFRx register.
DMADSCx bit = 1 ?
Transfer content from serial receive buffer
(depending on DTFRx register) to iRAM :
(MARx) SIRBnL, CBnRXL or UXnRX
Increment source pointer:
MARx MARx + 1
yes
(16 bit)
no
(8 bit)